Linear sweep circuit

Claim 2

In combination: a first timing capacitor; a first charging path connected to one side of said first timing capacitor for charging said first timing capacitor from a source of potential; a switching transistor, said first timing capacitor coupled in parallel across the switching path of said transistor; a bistable flip-flop circuit coupled to the control electrode of said switching transistor for turning said transistor on and off to correspondingly discharge and enable the charging of said timing capacitor; a capacitive boostrap circuit comprising a second capacitor coupled between said source of reference potential and an output terminal for providing a linear charging rate to said first capacitor; a field effect transistor having a gate electrode connected to said first timing capacitor so as to cause conduction of said field efFect transistor upon charging of said capacitor to a predetermined voltage level, and a variable input threshold Schmitt trigger logic circuit operative in response to the conduction of said field effect transistor to reset said bistable flip-flop circuit, and control sweep amplitude regardless of changes in sweep speed when the value of said timing capacitor is changed.

Claim 3

An electrical circuit for selectively generating sawtooth signal waves comprising in combination: a first capacitor having first and second terminals, said first terminal coupled to a source of potential and said second terminal connected to reference potential; a switching transistor having a base, emitter and collector electrodes, said collector and emitter electrodes connected in series circuit between said first terminal and reference potential; the improvement comprising in combination therewith; a field effect transistor having gate, source and drain electrodes, said gate electrode connected to said first terminal, said drain electrode connected to said source of potential; a J-K flip-flop circuit having set, reset, clear and clock input terminals and first and second output terminals, said set terminal connected to a positive reference potential, said clock pulse input terminal coupled to pulse source means, said clear input terminal coupled to reference potential, and said first output terminal coupled to said base electrode of said switching transistor; a Schmitt trigger logic circuit coupled to said source electrode and responsive to said sawtooth signal waves generated at said source electrode and having the output terminal thereof coupled to said reset input terminal of said J-K flip-flop circuit.

Claim 4

An electrical circuit for selectively generating sawtooth signal waves comprising in combination: a first capacitor having first and second terminals, said first terminal coupled to a source of potential and said second terminal connected to reference potential; a switching transistor having a base, emitter and collector electrodes, said collector and emitter electrodes connected in series circuit between said first terminal and reference potential; the improvement comprising in combination therewith; a field effect transistor having gate, source and drain electrodes, said gate electrode connected to said first terminal, said drain electrode connected to said source of potential; a J-K flip-flop circuit having set, reset, clear and clock input terminals and first and second output terminals, said set terminal connected to a positive reference potential, said clock pulse input terminal coupled to pulse source means, said clear input terminal coupled to reference potential, and said first output terminal coupled to said base electrode of said switching transistor; a Schmitt trigger logic circuit coupled to said source electrode and responsive to said sawtooth signal waves generated at said source electrode and having the output terminal thereof coupled to said reset input terminal of said J-K flip-flop circuit.

Claim 5

The combination of claim 1 wherein said first timing capacitor has a capacitance value of 47 pico farads for providing a sweep output signal having a period of in the order of 1 microsecond.

Claim 6

The combination of claim 1 wherein said first timing capacitor has a capacitance value of 1 microfarad for providing a sweep output signal of about 30 milliseconds duration.

Claim 7

A cathode ray sweep circuit for generating sweep output signals at the output terminal thereof in response to synchronizing pulses applied at the input terminal thereof comprising: a first capacitor; a switching transistor having collector, emitter and base electrodes, said collector and emitter electrodes connected across said first capacitor; means including a source of potential and a first variable resistor coupled in series circuit with said first capacitor; a second capacitor coupled in series circuit between said source of potential and said output terminal; a field effect transistor connected between said source of potential and said output terminal and having the gate electrode thereof coupled to said first capacitor; a Schmitt trigger logic circuit having an input terminal and an output terminal; a second variable resistor connected between said output terminal and reference potential and having the variable tap thereof connected to the input terminal of said Schmitt trigger logic circuit; and a J-K flip-flop circuit having set, reset, clear and clock input terminals and first and second output terminals, said set terminal connected to a positive reference potential, said clock pulse input terminal coupled to a synchronizing pulse source, said clear input terminal coupled to reference potential, said first output terminal coupled to said base of said switching transistor, and said reset terminal coupled to said output terminal of said Schmitt trigger logic circuit.

Claim 8

A cathode ray sweep circuit for generating sweep output signals at the output terminal thereof in response to synchronizing pulses applied at the input terminal thereof comprising: a first capacitor; a switching transistor having collector, emitter and base electrodes, said collector and emitter electrodes connected across said first capacitor; means including a source of potential and a first variable resistor coupled in series circuit with said first capacitor; a second capacitor coupled in series circuit between said source of potential and said output terminal; a field effect transistor connected between said source of potential and said output terminal and having the gate electrode thereof coupled to said first capacitor; a Schmitt trigger logic circuit having an input terminal and an output terminal; a second variable resistor connected between said output terminal and reference potential and having the variable tap thereof connected to the input terminal of said Schmitt trigger logic circuit; and a J-K flip-flop circuit having set, reset, clear and clock input terminals and first and second output terminals, said set terminal connected to a positive reference potential, said clock pulse input terminal coupled to a synchronizing pulse source, said clear input terminal coupled to reference potential, said first output terminal coupled to said base of said switching transistor, and said reset terminal coupled to said output terminal of said Schmitt trigger logic circuit.