Linear delay circuit

Claim 1

A LINEAR DELAY CIRCUIT COMPRISING IN COMBINATION: FIRST AND SECOND TRANSISTORS EACH HAVING BASE, EMITTER AND COLLECTOR ELECTRODES; MEANS CROSS-CONNECTING SAID BASE ELECTRODES AND SAID COLLECTOR ELECTRODES TO PROVIDE A BISTABLE CIRCUIT; AN INPUT TERMINAL CONNECTED TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR; AN INPUT TERMINAL CONNECTED TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR; THE EMITTER ELECTRODE OF SAID FIRST TRANSISTOR AND SAID SECOND TRANSISTOR BEING CONNECTED TO GROUND; AN OUTPUT TERMINAL CONNECTED TO THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR; A SAWTOOTH GENERATOR CONSISTING OF A THIRD TRANSISTOR HAVING BASE, EMITTER AND COLLECTOR ELECTRODES AND A TIMING CIRCUIT COMPRISING A SERIES CONNECTED RESISTOR AND CAPACITOR AND HAVING AN RC TIME CONSTANT; A JUNCTION FORMED BY ONE TERMINAL OF SAID RESISTOR AND ONE TERMINAL OF SAID CAPACITOR CONNECTED TO THE BASE ELECTRODE OF SAID THIRD TRANSISTOR, THE OTHER TERMINAL OF SAID CAPACITOR BEING CONNECTED TO GROUND; A COLLECTOR SUPPLY VOLTAGE MEANS HAVING ONE TERMINAL GROUNDED; THE COLLECTOR ELECTRODES OF SAID FIRST, SECOND AND THIRD TRANSISTORS CONNECTED TO ANOTHER TERMINAL OF SAID COLLECTOR SUPPLY VOLTAGE MEANS; A FIRST DIODE HAVING A CATHODE CONNECTED TO SAID COLLECTOR SUPPLY VOLTAGE MEANS AND AN ANODE TO THE RESISTOR OF SAID TIMING CIRCUIT; A SECOND DIODE HAVING AN ANODE CONNECTED TO THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR AND A CATHODE CONNECTED TO SAID JUNCTION OF THE TIMING CIRCUIT; A TRIGGER AMPLIFIER CONSISTING OF A FOURTH TRANSISTOR HAVING BASE, EMITTER AND COLLECTOR ELECTRODES, THE EMITTER ELECTRODE OF SAID FOURTH TRANSISTOR BEING CONNECTED TO GROUND AND THE COLLECTOR ELECTRODE THEREOF CONNECTED TO THE INPUT TERMINAL CONNECTED TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR OF THE BISTABLE CIRCUIT; A FEEDBACK RESISTOR, SAID FEEDBACK RESISTOR COUPLING AN OUTPUT OF THE SAWTOOTH GENERATOR AT THE EMITTER ELECTRODE OF THE THIRD TRANSISTOR TO THE BASE ELECTRODE OF SAID FOURTH TRANSISTOR WHEREBY THE SAWTOOTH GENERATOR OUTPUT OF THE SAWTOOTH GENERATOR IS APPLIED TO THE BASE ELECTRODE OF SAID FOURTH TRANSISTOR; A CONTROL VOLTAGE; AN INPUT RESISTOR HAVING ONE TERMINAL THEREOF CONNECTED TO THE BASE OF SAID FOURTH TRANSISTOR AND THE OTHER TERMINAL THEREOF TO SAID CONTROL VOLTAGE; AND MEANS FOR APPLYING A TRIGGER PULSE TO THE INPUT TERMINAL CONNECTED TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR; THE WIDTH OF THE PULSE OBTAINED AT THE SAID OUTPUT TERMINAL OF THE SECOND TRANSISTOR OF THE BISTABLE CIRCUIT BEING DETERMINED BY THE RATIO OF THE OHMIC VALUE OF THE FEEDBACK RESISTOR TO OHMIC VALUE OF THE INPUT RESISTOR TIMES THE RATIO OF THE VALUE OF THE CONTROL VOLTAGE TO THE VALUE OF THE COLLECTOR SUPPLY VOLTAGE MEANS TIMES THE RC TIME CONSTANT OF THE TIMING CIRCUIT OF THE SAWTOOTH GENERATOR.