Instruction translation control with extended address prefix decoding

Claim 2

In a data processing system wherein at least one memory is utilized to store instruction words containing an op-code field which contains either a normal op-code or a prefix code; and at least one address field; the improvement comprising the method of: reading one of said instruction words from said memory; detecting the bits of the op-code field read from memory, producing a first control signal if a normal op-code is detected or producing a second control signal if a prefix code is detected instead of said normal op-code; using said normal op-code to specify an operation to be performed and using said one address field to specify the location of an operand to be used in said operation in response to said first control signal; and, reading another portion of said instruction word in response to said second control signal to sense the op-code for an operation to be performed and to extend said one address field of said instruction word to include another portion of said instruction word to specify an address for any location in said memory.

Claim 3

In a data processing system having a first and second memory, at least one of the memories utilized to store both instruction and data words, each instruction word containing an op-code field which contains either an op-code or a prefix code and at least one address code field indicative of the ultimate location in one of said memories from which a word is read, to which a word is to be written, or the contents of which are to be modified, a designator bit in said instruction word defining whether a location in said first or second memory is to be addressed, an index bit defining whether the address field code is to be used to modify or to be modified by the content of the location specified therein, and a tabular bit defining whether said location specifies the ultimate memory location directly or specifies a location at which the address of the ultimate location is specified, control means responsive to said instruction word to perform any one or any combination of said functions to produce an address as specified by said instruction words, the improvement comprising the method of: reading one of said instruction words from memory; detecting the bits of the op-code field of said instruction word, producing a first control signal if a normal op-code is detected or producing a second coNtrol signal if a prefix code is detected in place of said normal op-code; executing normal usages of said normal op-code and said one address field respectively to define an operation to be performed by said control means and the memory location of an operand used in said operation in response to said first control signal; and, executing an extended address detecting operation whereby the bits of another portion of said instruction word are sensed to provide an op-code and the address found in said address code field is extended to include a further portion of said instruction word in response to said second control signal.

Claim 4

In a data processing system having a first and second memory, at least one of the memories utilized to store both instruction and data words, each instruction word containing an op-code field which contains either an op-code or a prefix code and at least one address code field indicative of the ultimate location in one of said memories from which a word is read, to which a word is to be written, or the contents of which are to be modified, a designator bit in said instruction word defining whether a location in said first or second memory is to be addressed, an index bit defining whether the address field code is to be used to modify or to be modified by the content of the location specified therein, and a tabular bit defining whether said location specifies the ultimate memory location directly or specifies a location at which the address of the ultimate location is specified, control means responsive to said instruction word to perform any one or any combination of said functions to produce an address as specified by said instruction words, the improvement comprising the method of: reading one of said instruction words from memory; detecting the bits of the op-code field of said instruction word, producing a first control signal if a normal op-code is detected or producing a second coNtrol signal if a prefix code is detected in place of said normal op-code; executing normal usages of said normal op-code and said one address field respectively to define an operation to be performed by said control means and the memory location of an operand used in said operation in response to said first control signal; and, executing an extended address detecting operation whereby the bits of another portion of said instruction word are sensed to provide an op-code and the address found in said address code field is extended to include a further portion of said instruction word in response to said second control signal.

Claim 5

The method of claim 2 including the step of; coding an instruction word to contain three address code fields and three sets of each of said designator, index and tabular bits.

Claim 6

The method of claim 3 including the steps of; specifying said first memory by one of said designator bits, specifying no modification of the addressing content with said index bit and the absence of said tabular bit, thereby defining a self-contained address in one of said address fields capable of addressing any location in said first memory.

Claim 7

The method of claim 3 including the steps of; specifying said first memory by one of said designator bits, specifying modification of the content of the location set forth in one of said address code fields with said index bit, and the absence of said tabular bit thereby defining modification of the content of said field by an extending augment in one of said address fields.

Claim 8

The method of claim 3 including the step of; specifying said second memory by one of said designator bits, specifying the ultimate location directly by said index bit and specifying no modification of the content of said location by said tabular bit, thereby defining in one of said address fields a self-contained address in said second memory.

Claim 9

The method of claim 3 including the steps of; specifying said second memory by one of said designator bits, specifying no augmentation by said index bit and specifying indirect addressing by said tabular bit, thereby defining an extended address form in one of said address fields capable of addressing any location in said second memory.

Claim 10

The method of claim 3 including the steps of; specifying the second memory by one of said designator bits, specifying indirect addressing by the index bit and specifying no modification by the tabular bit, thereby designating indirect addressing of said second memory.

Claim 11

The method of claim 3 including the steps of; specifying said first memory by one of said designator bits, specifying modification of the content of said location specified in one of said address field by said index bit and specifying indirect addressing by said tabular bit thereby defining an address field having an extended capacity to address any of the contents of said second memory in order to modify the contents of the location set forth and to address said first memory with said modified content.