US3656149A — Three frequency data separator

Claim 1

Independent Claim 191 words

In combination with a binary magnetic recording recovery device including a moving magnetic medium having recorded thereon flux orientations indicative of binary coded data, transducer means responsive to changes in the flux orientation of said moving magnetic medium for producing a read signal, peak detector means responsive to the maxima of the read signal for generating peak pulses, and phase-locked loop (PLL) means for generating a periodic frequency output having a prescribed phase relationship relative to the phase of the peak pulses, a decoder for decoding a self-clocking input information signal wherein a transition occurs in the middle of a bit cell representing a ''''1'''' and a transition occurs between bit cells representing two successive ''''0''s'''' comprising: a. first means for generating a ''''window'''' in the middle of a bit cell; b. second means responsive to said ''''window'''' for generating an output signal when there is a phase reversal in said ''''window'''' and no output signal when there is no phase reversal; c. and third means responsive to the output signal of said second means for generating a binary coded signal containing the three frequency encoded information of the input signal.

Claim 2

Dependent Claim 191 words

In combination with a binary magnetic recording recovery device including a moving magnetic medium having recorded thereon flux orientations indicative of binary coded data, transducer means responsive to changes in the flux orientation of said moving magnetic medium for producing a read signal, peak detector means responsive to the maxima of the read signal for generating peak pulses, and phase-locked loop (PLL) means for generating a periodic frequency output having a prescribed phase relationship relative to the phase of the peak pulses, a decoder for decoding a self-clocking input information signal wherein a transition occurs in the middle of a bit cell representing a ''''1'''' and a transition occurs between bit cells representing two successive ''''0''s'''' comprising: a. first means for generating a ''''window'''' in the middle of a bit cell; b. second means responsive to said ''''window'''' for generating an output signal when there is a phase reversal in said ''''window'''' and no output signal when there is no phase reversal; c. and third means responsive to the output signal of said second means for generating a binary coded signal containing the three frequency encoded information of the input signal.

Claim 3

Dependent Claim 39 words

A decoder as recited in claim 1 wherein said third means is responsive to said second means to generate a binary coded signal which is a Non-Return-To-Zero (NRZ) signal containing the three frequency encoded information of the input signal.

Claim 4

Dependent Claim 19 words

A decoder as recited in claim 2 including fourth means for generating clock pulses for clocking the Non-Return-To-Zero signal.

Claim 5

Dependent Claim 31 words

A decoder as recited in claim 1 including synchronizing means for synchronizing the phase of the PLL output signal in a prescribed manner with that of an input peak pulse signal.

Claim 6

Dependent Claim 115 words

A three frequency decoder for decoding a self-clocking input information signal wherein a transition occurs in the middle of a bit cell representing a ''''1'''' and a transition occurs between bit cells representing two successive ''''0'' s'''' comprising: a. first means for generating a ''''window'''' signal in the middle of a bit cell; b. second means responsive to said first means for generating an output signal when there is a phase reversal in said ''''window'''' signal and no output signal when there is no phase reversal; c. and third means responsive to the output signal of said second means for generating a binary coded signal containing the three frequency encoded information of the inpuT signal.

Claim 7

Dependent Claim 115 words

A three frequency decoder for decoding a self-clocking input information signal wherein a transition occurs in the middle of a bit cell representing a ''''1'''' and a transition occurs between bit cells representing two successive ''''0'' s'''' comprising: a. first means for generating a ''''window'''' signal in the middle of a bit cell; b. second means responsive to said first means for generating an output signal when there is a phase reversal in said ''''window'''' signal and no output signal when there is no phase reversal; c. and third means responsive to the output signal of said second means for generating a binary coded signal containing the three frequency encoded information of the inpuT signal.

Claim 8

Dependent Claim 52 words

A three frequency decoder as recited in claim 5 further comprising phase-locked loop (PLL) means for generating a periodic frequency signal which has a frequency of twice the data signal frequency, and also further comprising peak pulse generating means responsive to the maxima of a read signal for generating peak pulse signals.

Claim 9

Dependent Claim 38 words

A three frequency decoder as recited in claim 6 further comprising synchronizing means responsive to preamble binary signals for synchronizing in a prescribed manner the phase of the PLL output signals with that of the peak pulse signals.

Claim 10

Dependent Claim 47 words

A three frequency decoder as recited in claim 7 wherein the phase of the PLL output signal is synchronized with that of the peak pulse signal such that a leading edge of the peak pulse signal coincides in time with a trailing edge of a PLL signal.

Claim 11

Dependent Claim 104 words

A three frequency decoder as recited in claim 5 wherein said first, second and third means comprise synchronous/asynchronous flip-flops having set, reset (S, R) J and K input terminals and Q and Q output terminals and clock pulse (CP) terminal and having the following truth tables: Truth Table for Asynchronous Operation Set(s) Reset(R) Q output Q output L L H H L H H L H L L H H H Sync Inputs Control Truth Table for Synchronous Operation J K Q Q L H No change L L L H H H H L H L Toggle where L Low and H High

Claim 12

Dependent Claim 37 words

A three frequency decoder as recited in claim 5 including fourth means for generating clock pulses for clocking relative to the bit cell the binary coded signal containing the three frequency encoded information of the input signal.

Claim 13

Independent Claim 101 words

A method of decoding a self-clocking input information signal wherein a transition occurs in the middle of a bit cell representing a ''''1'''' and a transition occurs between bit cells representing two successive ''''0''s'''' comprising the steps of: a. generating a ''''window'''' signal in the middle of a bit cell; b. checking the ''''window'''' signal to determine the presence or absence of a phase reversal in the ''''window''''; c. generating a pulse signal if there is a phase reversal in the middle of the bit cell; d. and generating, in response to said pulse signal, a Non-Return-To-Zero (NRZ) binary coded signal.

Claim 14

Independent Claim 101 words

A method of decoding a self-clocking input information signal wherein a transition occurs in the middle of a bit cell representing a ''''1'''' and a transition occurs between bit cells representing two successive ''''0''s'''' comprising the steps of: a. generating a ''''window'''' signal in the middle of a bit cell; b. checking the ''''window'''' signal to determine the presence or absence of a phase reversal in the ''''window''''; c. generating a pulse signal if there is a phase reversal in the middle of the bit cell; d. and generating, in response to said pulse signal, a Non-Return-To-Zero (NRZ) binary coded signal.

Claim 15

Dependent Claim 28 words

A method of decoding a self-clocking input information signal as recited in claim 11 further comprising the step of generating clock pulse signals for clocking the NRZ signal.

Claim 16

Dependent Claim 33 words

A method of decoding a self-clocking input information signal as recited in claim 12 further comprising the step of generating a peak pulse signal in response to the maximum of a read signal.

Claim 17

Dependent Claim 38 words

A method of decoding a self-clocking input information signal as recited in claim 13 further comprising the step of generating a phase-locked loop (PLL) signal which has a frequency that is twice the frequency of the data signal.

Claim 18

Dependent Claim 43 words

A method of decoding a self-clocking input information signal as recited in claim 14 further comprising the step of generating a preamble binary signal for synchronizing in a prescribed manner the phase of the PLL signal with that of the peak pulse signal.

Claim 19

Dependent Claim 67 words

A method of decoding a self-clocking input information signal as recited in claim 15 wherein the phase of the PLL signal is synchronized with that of the peak pulse signal such that a leading edge of the peak pulse signal coincides in time with a trailing edge of a PLL signal and wherein the trailing edge of the PLL signal appears in the middle of the ''''window.''''

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1975-04-11	1975-10-11	1976-04-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1979-04-11	1979-10-11	1980-04-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1983-04-11	1983-10-11	1984-04-11	$7700.00	Window Closed / Lapsed

Three frequency data separator

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