Digital cycle system coordinator for traffic control system

Claim 1

In a system for coordinating the timing operation of a local traffic controller with timing signals generated at a master control station, said timing signals comprising first and second different frequency pulsating signals, a timing cycle being defined by the interval between successive phase coincidence between said signals, the improvement comprising means in the local controller for digitally generating signals indicative of precise increments of the timing cycle, said improvement including: frequency multiplier means for multiplying the frequency of said first signal by a multiplication factor corresponding to the number of the timing increments to be generated, logical control means for receiving the multiplied output of said frequency multiplier means, means responsive to the multiplied signal output of said logical control means for generating a tracking gate signal synchronized with a predetermined timing increment of said multiplied signal and at a frequency corresponding to said first signal, comparator means for comparing said tracking gate signal for time coincidence with said second signal, said comparator means generating a steering signal for said logical control means to cause said logical control means to generate a phase clock pulse corresponding to one of the increments of said timing cycle when the tracking and second signals are not in time coincidence and for feeding said multiplied signal to said means for generating a tracking gate signal when the tracking and second signals are in time coincidence.

Claim 7

A system for generating timing signals representing precise increments of a timing cycle comprising: means for generating first and second pulsating signals having a predetermined difference in frequency, the period between which said signals are in phase coincidence defining said timing cycle, means for multiplying said first pulsating signal by a factor determinative of the number of said timing Cycle increments in each cycle, counter means, offset transition control means, logical control means for receiving the multiplied signal and alternatively feeding said multiplied signal to said counter means or to said offset transition control means, said counter means being adapted to successively count to a number of bits equal to said multiplying factor, means responsive to said counter means for generating a tracking gate signal at the frequency of aid first pulsating signal and synchronized with a predetermined bit count of said counter means, and means for comparing said tracking gate signal and said second pulsating signal for time coincidence, said logical control means being responsive to the output of said comparing means and operating to feed said multiplied signal as a phase clock pulse (T Phi ) to said offset transition control means when said second pulsating signal and said gate signal are not in coincidence and to feed said multiplied signal (Tp ) to said counter means when said second pulsating signal and said tracking gate signal are in coincidence, whereby each time one of said phase clock pulses is fed to said offset transition control means, the timing of said tracking gate signal is delayed so as to tend to restore coincidence between said tracking gate signal and said second pulsating signal.

Claim 8

A system for generating timing signals representing precise increments of a timing cycle comprising: means for generating first and second pulsating signals having a predetermined difference in frequency, the period between which said signals are in phase coincidence defining said timing cycle, means for multiplying said first pulsating signal by a factor determinative of the number of said timing Cycle increments in each cycle, counter means, offset transition control means, logical control means for receiving the multiplied signal and alternatively feeding said multiplied signal to said counter means or to said offset transition control means, said counter means being adapted to successively count to a number of bits equal to said multiplying factor, means responsive to said counter means for generating a tracking gate signal at the frequency of aid first pulsating signal and synchronized with a predetermined bit count of said counter means, and means for comparing said tracking gate signal and said second pulsating signal for time coincidence, said logical control means being responsive to the output of said comparing means and operating to feed said multiplied signal as a phase clock pulse (T Phi ) to said offset transition control means when said second pulsating signal and said gate signal are not in coincidence and to feed said multiplied signal (Tp ) to said counter means when said second pulsating signal and said tracking gate signal are in coincidence, whereby each time one of said phase clock pulses is fed to said offset transition control means, the timing of said tracking gate signal is delayed so as to tend to restore coincidence between said tracking gate signal and said second pulsating signal.

Claim 16

A method for coordinating the timing opEration of a local traffic controller with a master control station comprising the steps of: generating reference and cycle control pulsating signals at the master station, said signals differing in frequency by an amount defining a timing cycle, transmitting said signals to said local controller, multiplying said reference signal by a factor defining increments of said timing cycle, generating a tracking gate signal synchronized with one of the timing increments of said multiplied signals and at the frequency of said reference signal, comparing said tracking gate signal and said cycle control signal for time coincidence, and logically gating out one pulse of said multiplied signal at a time, in response to a cycle control signal, as a clock signal, whenever the tracking gate signal and the cycle control signal are not in time coincidence.

Claim 17

A method for coordinating the timing opEration of a local traffic controller with a master control station comprising the steps of: generating reference and cycle control pulsating signals at the master station, said signals differing in frequency by an amount defining a timing cycle, transmitting said signals to said local controller, multiplying said reference signal by a factor defining increments of said timing cycle, generating a tracking gate signal synchronized with one of the timing increments of said multiplied signals and at the frequency of said reference signal, comparing said tracking gate signal and said cycle control signal for time coincidence, and logically gating out one pulse of said multiplied signal at a time, in response to a cycle control signal, as a clock signal, whenever the tracking gate signal and the cycle control signal are not in time coincidence.