Chirp pulse generating circuits

Claim 2

A Chirp pulse generating circuit comprising a constant-K, low-pass filter-type delay line comprising serially connected inductor and shunt-connected capacitor elements and, furthermore, having input and output ports, said inductor and capacitor elements having values to provide said line, when viewed from said input port to said output port, with a substantially constant impedance characteristic and a progressively changing time delay characteristic, a gated energy source connected to all of said elements of one type to charge those elements, when said source is enabled, to energy levels which levels when viewed as dispersed on said line have a sine wave envelope, an impedance matching resistor connected across said input port, and an impedance matching load connected across said output port.

Claim 3

A circuit in accordance with claim 1 in which said source is a voltage source having output leads connected to said delay line capacitive elements, respectively.

Claim 4

A circuit in accordance with claim 2 in which the difference in time delay from section to section of said line is a constant.

Claim 5

A circuit in accordance with claim 1 wherein each of said inductor elements in said delay line has a relatively large valued capacitor connected in series with it, said large valued capacitors having a negligible effect within the passband of said delay line.

Claim 6

A circuit in accordance with claim 4 in which said source is a current source having sets of output leads connected to said delay line inductor elements, respectively.

Claim 7

A circuit in accordance with claim 5 in which the difference in time delay from section to section of said line is a constant.

Claim 8

A circuit for generating Chirp pulses, said circuit comprising a two-port low-pass filter-type delay line comprising inductor and capacitor elements and, furthermore, having a constant-K characteristic in a passband at least equal to the bandwidth of said Chirp pulses, said inductor and capacitor elements having values to provide said line, when viewed from a first of said ports to the other of said ports, with a substantially constant impedance characteristic and a progressively changing time delay characteristic, a gated energy source connected to all of said elements of one type to charge those elements, when said source is enabled, to energy levels which levels when viewed as dispersed on said line have a sine wave envelope, an impedance matching resistor connected across said first port, and an impedance matching load connected across said other port.

Claim 9

A circuit for generating Chirp pulses, said circuit comprising a two-port low-pass filter-type delay line comprising inductor and capacitor elements and, furthermore, having a constant-K characteristic in a passband at least equal to the bandwidth of said Chirp pulses, said inductor and capacitor elements having values to provide said line, when viewed from a first of said ports to the other of said ports, with a substantially constant impedance characteristic and a progressively changing time delay characteristic, a gated energy source connected to all of said elements of one type to charge those elements, when said source is enabled, to energy levels which levels when viewed as dispersed on said line have a sine wave envelope, an impedance matching resistor connected across said first port, and an impedance matching load connected across said other port.

Claim 10

A circuit in accordance with claim 7 in which said source is a voltage source having output leads connected to said delay line capacitive elements, respectively.

Claim 11

A circuit in accordance with claim 8 in which the difference in time delay from section to section of said line is a constant.

Claim 12

A circuit in accordance with claim 7 wherein each of said inductor elements in said delay line has a relatively large valued capacitor connected in series with it, said large valued capacitors having a negligible effect withIn the passband of said delay line.

Claim 13

A circuit in accordance with claim 10 in which said source is a current source having sets of output leads connected to said delay line inductor elements, respectively.

Claim 14

A circuit in accordance with claim 11 in which the difference in time delay from section to section of said line is a constant.

Claim 15

A Chirp pulse generating circuit comprising an incrementally time dispersive delay line comprising inductor and capacitor elements and, furthermore, having input and output ports, a gated energy source connected to all of said elements of one type to charge those elements, when said source is enabled, to energy levels which levels when viewed as dispersed on said line have a sine wave envelope, an impedance matching resistor connected across said input port, and an impedance matching load connected across said output port.

Claim 16

A Chirp pulse generating circuit comprising an incrementally time dispersive delay line comprising inductor and capacitor elements and, furthermore, having input and output ports, a gated energy source connected to all of said elements of one type to charge those elements, when said source is enabled, to energy levels which levels when viewed as dispersed on said line have a sine wave envelope, an impedance matching resistor connected across said input port, and an impedance matching load connected across said output port.

Claim 17

A circuit in accordance with claim 13 in which said source is a voltage source having output leads connected to said delay line capacitive elements, respectively.

Claim 18

A circuit in accordance with claim 14 in which the difference in time delay from section to section of said line is a constant.

Claim 19

A circuit in accordance with claim 13 wherein each of said inductor elements in said delay line has a relatively large valued capacitor connected in series with it, said large valued capacitors having a negligible effect within the passband of said delay line.

Claim 20

A circuit in accordance with claim 16 in which said source is a current source having sets of output leads connected to said delay line inductor elements, respectively.

Claim 21

A circuit in accordance with claim 16 in which the difference in time delay from section to section of said line is a constant.