Non-linear decoder with linear and non-linear ladder attenuators

Claim 2

A digital-to-analog decoder for a multi-digit number adapted to produce an analog output with a voltage amplitude characteristic which is symmetric with respect to a zero abscissa, the positive and negative half-characteristics comprising three parts: a first linear part near the origin, a logarithmic part, a second linear part, said both linear parts being tangential extensions of the ends of said logarithmic part; said decoder comprising a digit register and two ladder attenuators, first decoding means for decoding the most significant digits of said number, second decoding means for decoding the least significant digits, a first group of current generator means controlled by the signals corresponding to the least significant digits, a second group of current generator means controlled by the output signals of said second decoding means, electronic gate means controlled responsive to the output signals of said first decoding means operatively connected between the current generators and the two ladder attenuators such that the generated current is selectively gated to said ladder attenuators and means for taking said analog voltage from between output terminals on the two ladder attenuators to form the voltage amplitude characteristic representative of said number.

Claim 3

The decoder of claim 1 wherein said first and second ladder attenuators are identical.

Claim 4

The decoder of claim 1 wherein said register comprises a seven digit register, four of said digits are said most significant digits, and the remaining three of said digits are said least significant digits.

Claim 5

The decoder of claim 1 and means responsive to the value of the most significant digits for selecting the polarity of said signal.

Claim 6

A decoder of binary numbers comprising seven digits comprising, means responsive to the most significant digits of a a number of selecting the polarity of an output analog voltage, means responsive to the other digits of said number for providing the amplitude of the output analog voltage measured on both sides of the level of the nil voltage to produce a characteristic symmetrical with respect to the zero abscissa point, the characteristic comprising a logarithmic part and linear parts at both extensions of said logarithmic part, register means for storing the binary numbers to be decoded, first decoder means for decoding the four most significant digits of the said binary number, second decoder means for decoding the other digits of the same binary number, two identical ladder attenuator means, each attenuator means comprising five identical cells, a first multiplicity of current generator means controlled by the output signals of the second decoder means when the binary number corresponds to the logarithmic part, and a second multiplicity of current generator means controlled by the four least significant digits of the binary number when the binary number corresponds to a linear part, and a plurality of electronic gate means arranged between the current generators and the two attenuators and controlled by the output signals of the first decoder means, a first additional generator means associated with the first multiplicity of current generator means, means for injecting the current of said first multiplicity of current generator means into the other ladder attenuator through two of said electronic gate means controlled by the signal corresponding to the most significant digit of the binary number, a second additional current generator means associated with the second multiplicity of current generator means which supplies a current only for the binary numbers corresponding to the one linear part, and means for taking the decoded voltage from between the output terminals of the two ladder attenuator means.

Claim 7

A decoder of binary numbers comprising seven digits comprising, means responsive to the most significant digits of a a number of selecting the polarity of an output analog voltage, means responsive to the other digits of said number for providing the amplitude of the output analog voltage measured on both sides of the level of the nil voltage to produce a characteristic symmetrical with respect to the zero abscissa point, the characteristic comprising a logarithmic part and linear parts at both extensions of said logarithmic part, register means for storing the binary numbers to be decoded, first decoder means for decoding the four most significant digits of the said binary number, second decoder means for decoding the other digits of the same binary number, two identical ladder attenuator means, each attenuator means comprising five identical cells, a first multiplicity of current generator means controlled by the output signals of the second decoder means when the binary number corresponds to the logarithmic part, and a second multiplicity of current generator means controlled by the four least significant digits of the binary number when the binary number corresponds to a linear part, and a plurality of electronic gate means arranged between the current generators and the two attenuators and controlled by the output signals of the first decoder means, a first additional generator means associated with the first multiplicity of current generator means, means for injecting the current of said first multiplicity of current generator means into the other ladder attenuator through two of said electronic gate means controlled by the signal corresponding to the most significant digit of the binary number, a second additional current generator means associated with the second multiplicity of current generator means which supplies a current only for the binary numbers corresponding to the one linear part, and means for taking the decoded voltage from between the output terminals of the two ladder attenuator means.

Claim 8

A digital-to-analog decoder of seven-digiT binary numbers the most significant of which characterizes the polarity of the analog voltage output, the other digits characterizing the amplitude of the voltage with respect to the zero voltage, said decoder forming a characteristic curve which is symmetric with respect to zero abscissa, each half-characteristic comprising three parts: a first linear part near the origin, a logarithmic part, a second linear part, said both linear parts being tangential to ends of said logarithmic part; the invention comprising a seven-digit register, two identical ladder attenuators, one for developing each half-characteristic, first decoding means for decoding the four most significant digits and producing output signals, second decoding means for decoding the three other digits and producing output signals, a first group of current generators controlled by the signals corresponding to the four least significant digits of the codes, a second group of current generators controlled by the output signals of second decoding means, a multiplicity of electronic gates controlled by the output signals of said first decoding means and operatively connected between the current generators and the two ladder attenuators such that the generated current is selectively gated to said ladder attenuators; whereby the decoded analog voltage following said characteristic is taken between terminals of the two ladder attenuators.

Claim 9

A digital-to-analog decoder of seven-digiT binary numbers the most significant of which characterizes the polarity of the analog voltage output, the other digits characterizing the amplitude of the voltage with respect to the zero voltage, said decoder forming a characteristic curve which is symmetric with respect to zero abscissa, each half-characteristic comprising three parts: a first linear part near the origin, a logarithmic part, a second linear part, said both linear parts being tangential to ends of said logarithmic part; the invention comprising a seven-digit register, two identical ladder attenuators, one for developing each half-characteristic, first decoding means for decoding the four most significant digits and producing output signals, second decoding means for decoding the three other digits and producing output signals, a first group of current generators controlled by the signals corresponding to the four least significant digits of the codes, a second group of current generators controlled by the output signals of second decoding means, a multiplicity of electronic gates controlled by the output signals of said first decoding means and operatively connected between the current generators and the two ladder attenuators such that the generated current is selectively gated to said ladder attenuators; whereby the decoded analog voltage following said characteristic is taken between terminals of the two ladder attenuators.