Patent US3652998A successfully refreshed from Google Patents.
US3652998A
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Interleavers
Assignee: Motorola Solutions Inc
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Filing: 1970-03-01
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Granted: 1972-03-28
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Expires: 1990-03-01
Abstract
Abstract Interleavers, which spread the bits in a group of length B in the input sequence so that any pair are at least N bits apart in the output sequence, in which delaying circuitry (e.g., one or more shift registers) cooperates with control circuitry to define a plurality of delay paths, each of which is of constant length, the number of such paths being equal to the period, P, of the interleaver (where 2 < OR = P<BN/2). The control circuitry classifies any P successive bits of the input sequence to the P different delay paths, the bits being classified to any such path being spaced P bits apart. The output sequence is derived by sequentially selecting bits from the various delay paths.
Inventors
- 👤 George David Forney Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/762; H; H03; H03M; H03M13/00; H03M13/27
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
168 words
Apparatus for interleaving an input sequence of information signals so that any two input signals separated by B or fewer signals will be separated by N or more signals in an output sequence, comprising control circuitry and delaying circuitry of predetermined storage capacity, defining a number P of delay paths, P having a value of at least 2 and less than BN/2, each path having a fixed length equal to a predetermined number of intervals of said input sequence, certain of said paths being longer than other of said paths, said control circuitry including means to classify any P successive information signals respectively to the P different delay paths in accordance with a fixed, predetermined order, the signals classified to each path being spaced a period of P intervals apart, and means to deliver an output sequence of information signals derived from the various delay paths, P being the least common multiple of P1, P2...Pn, said apparatus comprising a cascade of n constituent interleavers having periods P1, P2...Pn.
Claim 2
Dependent Claim
168 words
Apparatus for interleaving an input sequence of information signals so that any two input signals separated by B or fewer signals will be separated by N or more signals in an output sequence, comprising control circuitry and delaying circuitry of predetermined storage capacity, defining a number P of delay paths, P having a value of at least 2 and less than BN/2, each path having a fixed length equal to a predetermined number of intervals of said input sequence, certain of said paths being longer than other of said paths, said control circuitry including means to classify any P successive information signals respectively to the P different delay paths in accordance with a fixed, predetermined order, the signals classified to each path being spaced a period of P intervals apart, and means to deliver an output sequence of information signals derived from the various delay paths, P being the least common multiple of P1, P2...Pn, said apparatus comprising a cascade of n constituent interleavers having periods P1, P2...Pn.
Claim 3
Dependent Claim
51 words
The apparatus of claim 1 wherein the delay paths in one constituent interleaver have lengths approximately equal to 0, D, 2D,..., (Q1-1)D and the delay paths of the second constituent interleaver have lengths approximately equal to 0, Q, D, 2Q1D, ..., (Q2-1)Q1D where the product of Q1 and Q2 is P.
Claim 4
Dependent Claim
38 words
The apparatus of claim 1 wherein said delaying circuitry comprises at least two stages of delay circuits connectable in cascade such that delay circuits of the first stage are periodically connected to delay circuits of the second stage.
Claim 5
Dependent Claim
162 words
Apparatus for interleaving an input sequence of information signals so that any two input signals separated by B or fewer signals will be separated by N or more signals in an output sequence, comprising control circuitry and delaying circuitry of predetermined storage capacity, defining a number P of delay paths, P having a value of at least 2 and less than BN/2, each path having a fixed length equal to a predetermined number of intervals of said input sequence, certain of said paths being longer than other of said paths, at least two of said delay paths extending through a common portion of said delaying circuitry, said control circuitry including means to classify any P successive information signals respectively to the P different delay paths in accordance with a fixed, predetermined order, the signals classified to each path being spaced a period of P intervals apart, and means to deliver an output sequence of information signals derived from the various delay paths.
Claim 6
Dependent Claim
162 words
Apparatus for interleaving an input sequence of information signals so that any two input signals separated by B or fewer signals will be separated by N or more signals in an output sequence, comprising control circuitry and delaying circuitry of predetermined storage capacity, defining a number P of delay paths, P having a value of at least 2 and less than BN/2, each path having a fixed length equal to a predetermined number of intervals of said input sequence, certain of said paths being longer than other of said paths, at least two of said delay paths extending through a common portion of said delaying circuitry, said control circuitry including means to classify any P successive information signals respectively to the P different delay paths in accordance with a fixed, predetermined order, the signals classified to each path being spaced a period of P intervals apart, and means to deliver an output sequence of information signals derived from the various delay paths.
Claim 7
Dependent Claim
25 words
The apparatus of claim 4 wherein said delaying circuitry includes storage means comprising an extended length of signal storage positions through which information signals progress.
Claim 8
Dependent Claim
30 words
The apparatus of claim 5 wherein said storage means comprises a number of storage elements each having an extended length of untapped signal storage positions through which information signals progress.
Claim 9
Dependent Claim
15 words
The apparatus of claim 6 wherein the majority of said storage elements have equal length.
Claim 10
Dependent Claim
13 words
The apparatus of claim 5 wherein said storage means comprises a shift register.
Claim 11
Dependent Claim
34 words
The apparatus of claim 4 wherein said control circuitry defines said delay paths by establishing at least two sets of connections between storage elements of said delaying circuitry and said input and output terminals.
Claim 12
Dependent Claim
52 words
The apparatus of claim 9 wherein at least one of said connections is a feedback connection such that at least one information signal passes through the same storage element of said delaying circuitry twice, enabling a delay path to be defined which is longer than the overall delay of said delaying circuitry.
Claim 13
Dependent Claim
16 words
The apparatus of claim 9 wherein said delaying circuitry has a common input or output terminal.
Claim 14
Dependent Claim
58 words
The apparatus of claim 6 wherein said delaying circuitry comprises P separate shift registers, one of which may have length zero, and said control circuitry comprises means for separating said input sequence into P different subsequences, passing each subsequence through a different said shift register, and recombining the outputs of said shift registers to form said output sequence.
Claim 15
Dependent Claim
76 words
The apparatus of claim 6 wherein said delaying circuitry comprises at least one untapped shift register, and said control circuitry comprises a sequential circuit of period P arranged to cycle in synchronism with said input information sequence through P distinct states and gating means responsive to said states arranged to form P distinct connection patterns between the input and output terminals of said register or registers and the input and output terminals of the interleaving apparatus.
Claim 16
Dependent Claim
61 words
The apparatus of claim 13 wherein said delaying circuitry consists of P-1 Untapped shift registers of equal length arranged in a single chain, and said connection patterns include beyond the chain patterns only connections from said input terminal of said apparatus to some said shift register input and from said output terminal of said apparatus to some said shift register output.
Claim 17
Dependent Claim
31 words
The apparatus of claim 13 wherein said delaying circuitry consists of (P-1)/2 untapped shift registers of equal length arranged in a single chain, and (P-1)/2 of said connection patterns involve feedback.
Claim 18
Dependent Claim
54 words
The apparatus of claim 5 wherein said delaying circuitry comprises one long untapped shift register and a second storage element, said second element having much smaller storage capacity than said long register, and said control circuitry includes means for clocking said long register more than once upon the arrival of each said information signal.
Claim 19
Dependent Claim
14 words
The apparatus of claim 16 wherein said second storage element is a single flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-28 | 1975-09-27 | 1976-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-28 | 1979-09-27 | 1980-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-28 | 1983-09-27 | 1984-03-28 | $7700.00 | Window Closed / Lapsed |