Patent US3648079A successfully refreshed from Google Patents.
US3648079A
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US
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High-speed sense latch circuit
Assignee: Cogar Corp
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Filing: 1970-07-10
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Granted: 1972-03-07
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Expires: 1990-07-10
Abstract
Abstract A sense latch circuit having a short access time. The latch output switches state rapidly due to the incorporation of a minimum number of logic stages between the sense inputs and the output drive stage, thereby introducing a minimum number of delays. Nonsaturable logic circuits are utilized to allow fast switching. At the inputs of the sense latch circuit, the high DC levels of the sense signals are reduced in magnitude for application to an ECL circuit switch with the use of diodes and resistor dividers. This arrangement allows for large temperature variations without saturating any of the logic stages.
Inventors
- 👤 Richard W Bryant
- 👤 George K Tu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C7/00; G11C7/06; G11C7/062; G11C7/065; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
314 words
A high-speed sense latch circuit comprising a pair of sense input termInals, a set input terminal, a reset input terminal, a latch output terminal, a current switch having two input terminals and an output terminal, semiconductor voltage dropping means and resistor voltage divider network means connected between each of the sense input terminals and a respective one of said current switch input terminals for translating the DC voltage level at each of said sense input terminals to a reduced voltage level at each of said current switch input terminals, means for controlling a first signal at said current switch output terminal responsive to both the application of a set pulse to said set input terminal together with the application of a first sense signal to said sense input terminals and the absence of the application of a set pulse to said set input terminal, and for controlling a second signal at said current switch output terminal responsive to the application of a set pulse to said set input terminal together with the application of a second sense signal to said sense input terminals, means for generating a current responsive to the appearance of said first signal at said current switch output terminal, means for conducting said current when generated and responsive to said current for causing a first potential to appear at said latch output terminal and responsive to the absence of said current for causing a second potential to appear at said latch output terminal, feedback means responsive to said second potential appearing at said latch output terminal for bypassing subsequently generated current from said conducting means to maintain said latch output terminal at said second potential even when said first signal is thereafter developed at said current switch output terminal, and means responsive to the application of a reset pulse to said reset input terminal for turning off said feedback bypassing means.
Claim 2
Dependent Claim
314 words
A high-speed sense latch circuit comprising a pair of sense input termInals, a set input terminal, a reset input terminal, a latch output terminal, a current switch having two input terminals and an output terminal, semiconductor voltage dropping means and resistor voltage divider network means connected between each of the sense input terminals and a respective one of said current switch input terminals for translating the DC voltage level at each of said sense input terminals to a reduced voltage level at each of said current switch input terminals, means for controlling a first signal at said current switch output terminal responsive to both the application of a set pulse to said set input terminal together with the application of a first sense signal to said sense input terminals and the absence of the application of a set pulse to said set input terminal, and for controlling a second signal at said current switch output terminal responsive to the application of a set pulse to said set input terminal together with the application of a second sense signal to said sense input terminals, means for generating a current responsive to the appearance of said first signal at said current switch output terminal, means for conducting said current when generated and responsive to said current for causing a first potential to appear at said latch output terminal and responsive to the absence of said current for causing a second potential to appear at said latch output terminal, feedback means responsive to said second potential appearing at said latch output terminal for bypassing subsequently generated current from said conducting means to maintain said latch output terminal at said second potential even when said first signal is thereafter developed at said current switch output terminal, and means responsive to the application of a reset pulse to said reset input terminal for turning off said feedback bypassing means.
Claim 3
Dependent Claim
35 words
A high-speed sense latch circuit in accordance with Claim 1 wherein said conducting means and said feedback bypassing means each includes at least one semiconductor logic stage and means for preventing saturation upon conduction thereof.
Claim 4
Dependent Claim
100 words
A high-speed sense latch circuit in accordance with claim 2 wherein said first potential at said latch output terminal is high relative to said second potential and said feedback bypassing means includes first transistor means for generating a low-level signal responsive to said first potential appearing at said latch output terminal, second transistor means for generating a low-level signal responsive to the application of a reset pulse to said reset input terminal, and means coupled to said conducting means for diverting current therefrom responsive to the generation of a low-level signal by either of said first and second transistor means.
Claim 5
Dependent Claim
266 words
A high-speed sense latch monolithic integrated circuit comprising a pair of sense input terminals, a set input terminal, a reset input terminal, a latch output terminal, a current switch having two input terminals and an output terminal, means for controlling a first signal at said current switch output terminal responsive to both the application of a set pulse to said set input terminal together with the application of a first sense signal to said sense input terminals and the absence of the application of a set pulse to said set input terminal, and for controlling a second signal at said current switch output terminal responsive to the application of a set pulse to said set input terminal together with the application of a second sense signal to said sense input terminals, means responsive to the appearance of said first signal at said current switch output terminal for causing a first potential to appear at said latch output terminal and responsive to the appearance of said second signal at said current switch output terminal for causing a second potential to appear at said latch output terminal, feedback means responsive to said second potential appearing at said latch output terminal for maintaining said latch output terminal at said second poTential even when said first signal is thereafter developed at said current switch output terminal, and means responsive to the application of a reset pulse to said reset input terminal for turning off said feedback means, said potential-causing means and said feedback means each including at least one semiconductor logic stage and means for preventing saturation upon conduction thereof.
Claim 6
Dependent Claim
266 words
A high-speed sense latch monolithic integrated circuit comprising a pair of sense input terminals, a set input terminal, a reset input terminal, a latch output terminal, a current switch having two input terminals and an output terminal, means for controlling a first signal at said current switch output terminal responsive to both the application of a set pulse to said set input terminal together with the application of a first sense signal to said sense input terminals and the absence of the application of a set pulse to said set input terminal, and for controlling a second signal at said current switch output terminal responsive to the application of a set pulse to said set input terminal together with the application of a second sense signal to said sense input terminals, means responsive to the appearance of said first signal at said current switch output terminal for causing a first potential to appear at said latch output terminal and responsive to the appearance of said second signal at said current switch output terminal for causing a second potential to appear at said latch output terminal, feedback means responsive to said second potential appearing at said latch output terminal for maintaining said latch output terminal at said second poTential even when said first signal is thereafter developed at said current switch output terminal, and means responsive to the application of a reset pulse to said reset input terminal for turning off said feedback means, said potential-causing means and said feedback means each including at least one semiconductor logic stage and means for preventing saturation upon conduction thereof.
Claim 7
Dependent Claim
102 words
A high-speed sense latch circuit in accordance with claim 4 wherein said first potential at said latch output terminal is high relative to said second potential and said feedback means includes first transistor means for generating a low-level signal responsive to said first potential appearing at said latch output terminal, second transistor means for generating a low-level signal responsive to the application of a reset pulse to said reset input terminal, and means responsive to the generation of a low-level signal by either of said first and second transistor means for enabling said first potential to appear at said latch output terminal.
Claim 8
Dependent Claim
129 words
A high-speed sense latch circuit in accordance with claim 5 further including resistor divider means and semiconductor voltage-dropping means connected between each of the sense input terminals and a respective one of said current switch input terminals for translating the DC voltage at each of said sense input terminals to a different DC voltage at the respective one of said current switch input terminals. 7 A high-speed sense latch circuit in accordance with claim 4 further including resistor divider means and semiconductor voltage-dropping means connected between each of the sense input terminals and a respective one of said current switch input terminals for translating the DC voltage at each of said sense input terminals to a different DC voltage at the respective one of said current switch input terminals.
Claim 9
Dependent Claim
264 words
A high-speed sense latch circuit comprising a pair of sense input terminals, a set input terminal, a reset input terminal, a latch output terminal, switching means having two input terminals and an output terminal, means for controlling a first signal at said switching means output terminal responsive to both the application of a set pulse to said set input terminal together with the application of a first sense signal to said sense input terminals and the absence of the application of a set pulse to said set input terminal, and for controlling a second signal at said switching means output terminal responsive to the application of a set pulse to said set input terminal together with the application of a second sense signal to said sense input terminals, means responsive to the appearance of said first signal at said switching means output terminal for causing a first potential to appear at said latch output terminal and responsive to the appearance of said second signal at said switching means output terminal for causing a second potential to appear at said latch output terminal, feedback means responsive to said second potential appearing at said latch output terminal for maintaining said latch output terminal at said second potential even when said first signal is thereafter developed at said switching means output terminal, and means responsive to the application of a reset pulse to said reset input terminal for turning off said feedback means, said potential causing means and said feedback means each including at least one semiconductor logic stage and means for preventing saturation upon conduction thereof.
Claim 10
Dependent Claim
264 words
A high-speed sense latch circuit comprising a pair of sense input terminals, a set input terminal, a reset input terminal, a latch output terminal, switching means having two input terminals and an output terminal, means for controlling a first signal at said switching means output terminal responsive to both the application of a set pulse to said set input terminal together with the application of a first sense signal to said sense input terminals and the absence of the application of a set pulse to said set input terminal, and for controlling a second signal at said switching means output terminal responsive to the application of a set pulse to said set input terminal together with the application of a second sense signal to said sense input terminals, means responsive to the appearance of said first signal at said switching means output terminal for causing a first potential to appear at said latch output terminal and responsive to the appearance of said second signal at said switching means output terminal for causing a second potential to appear at said latch output terminal, feedback means responsive to said second potential appearing at said latch output terminal for maintaining said latch output terminal at said second potential even when said first signal is thereafter developed at said switching means output terminal, and means responsive to the application of a reset pulse to said reset input terminal for turning off said feedback means, said potential causing means and said feedback means each including at least one semiconductor logic stage and means for preventing saturation upon conduction thereof.
Claim 11
Dependent Claim
102 words
A high-speed sense latch circuit in accordance with claim 8 wherein said first potential at said latch output terminal is high relative to said second potential and said feedback means includes first transistor means for generating a low-level signal responsive to said first potential appearing at said latch output terminal, second transistor means for generating a low-level signal responsive to the application of a reset pulse to said reset input terminal, and means responsive to the generation of a loW-level signal by either of said first and second transistor means for enabling said first potential to appear at said latch output terminal.
Claim 12
Dependent Claim
64 words
A high-speed sense latch circuit in accordance with claim 9 further including resistor divider means and semiconductor voltage-dropping means connected between each of the sense input terminals and a respective one of said switching means input terminals for translating the DC voltage at each of said sense input terminals to a different DC voltage at the respective one of said switching means input terminals.
Claim 13
Dependent Claim
64 words
A high-speed sense latch circuit in accordance with claim 8 further including resistor divider means and semiconductor voltage-dropping means connected between each of the sense input terminals and a respective one of said switching means input terminals for translating the DC voltage at each of said sense input terminals to a different DC voltage at the respective one of said switching means input terminals.
Claim 14
Dependent Claim
292 words
A high-speed latch circuit comprising a pair of sense input terminals, a set input terminal, a reset input terminal, a latch output terminal switching means having two input terminals and an output terminal, means for controlling a first signal at said switching means output terminals responsive to both the application of a set pulse to said set input terminal together with the application of a first sense signal to said sense input terminals and the absence of the application of a set pulse to said set input terminal, controlling and for controlling a second signal at said switching means output terminal responsive to the application of a set pulse to said set input terminal together with the application of a second sense signal to said sense input terminals, means responsive to the appearance of said first signal at said switching means output terminal for causing a first potential to appear at said latch output terminal and responsive to the appearance of said second signal at said switching means output terminal for causing a second potential to appear at said latch output terminal, feedback means responsive to said second potential appearing at said latch output terminal for maintaining said latch output terminal at said second potential even when said first signal is thereafter developed at said switching means output terminal, and means responsive to the application of a reset pulse to said reset input terminal for turning off said feedback means, resistor divider means and semiconductor voltage-dropping means connected between each of the sense input terminals and a respective one of said switching means input terminals for translating the DC voltage at each of said sense input terminals to a different DC voltage at the respective one of said switching means input terminals.
Claim 15
Dependent Claim
292 words
A high-speed latch circuit comprising a pair of sense input terminals, a set input terminal, a reset input terminal, a latch output terminal switching means having two input terminals and an output terminal, means for controlling a first signal at said switching means output terminals responsive to both the application of a set pulse to said set input terminal together with the application of a first sense signal to said sense input terminals and the absence of the application of a set pulse to said set input terminal, controlling and for controlling a second signal at said switching means output terminal responsive to the application of a set pulse to said set input terminal together with the application of a second sense signal to said sense input terminals, means responsive to the appearance of said first signal at said switching means output terminal for causing a first potential to appear at said latch output terminal and responsive to the appearance of said second signal at said switching means output terminal for causing a second potential to appear at said latch output terminal, feedback means responsive to said second potential appearing at said latch output terminal for maintaining said latch output terminal at said second potential even when said first signal is thereafter developed at said switching means output terminal, and means responsive to the application of a reset pulse to said reset input terminal for turning off said feedback means, resistor divider means and semiconductor voltage-dropping means connected between each of the sense input terminals and a respective one of said switching means input terminals for translating the DC voltage at each of said sense input terminals to a different DC voltage at the respective one of said switching means input terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-07 | 1975-09-06 | 1976-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-07 | 1979-09-06 | 1980-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-07 | 1983-09-06 | 1984-03-07 | $7700.00 | Window Closed / Lapsed |