Data regeneration scheme without using memory sense amplifiers

Claim 2

In a memory made of a matrix of stored-charge memory cells each addressed by the selection of a plurality of lines out of a grid of addressing lines for the matrix, a data regeneration scheme for periodically restoring the data stored in the memory cell without reading the data out through the sense amplifiers of the memory, comprising: read means for reading data stored in any given cell out onto one of the plurality of lines for addressing the cell; restore cell means coupled to said one of the plurality of lines for taking the data read out onto said one of the plurality of lines directly off said one line without reading the data out through a sense amplifier and temporarily storing the data so taken; and write means for writing the data stored in the restore cell means back into the given storage cell.

Claim 3

The matrix of claim 1 wherein said storage cells and restore cells are three device cells each with a first device storing data in the form of charge on one of its interelectrode capacitances; a second device for charging and discharging the interelectrode capacitance of the first driver onto said one of the plurality of lines for addressing the cell; and a third device for placing a signal on said one of the plurality of lines indicative of the data stored in the interelectrode capacitance of said first device.

Claim 4

The matrix of claim 2 including means for rendering the third device of said storage cell and the second device of said restore cell conductive at the same time to transfer the data stored in the storage cell into the restore cell; and means for rendering the second device of said storage cell and the third device of said restore cell conductive at the same time to transfer data placed in the restore cell back into the storage cell whereby the data on the storage cells can be periodically restored.

Claim 5

The matrix of claim 3 wherein said devices are field effect transistors.

Claim 6

A word-oriented matrix of stored-charge memory cells comprising: a. a plurality of word and bit lines; b. a plurality of stored charge storage cells each having i. a first semiconductor device which is rendered conductive or nonconductive to store data by the changing of the charge level on one of its interelectrode capacitances; ii. a second semiconductor device which couples said one of the interelectrode capacitances to one of the bit lines for charging and discharging said interelectrode capacitance in response to signals on a first of the word lines; iii. a third semiconductor device which forms a series circuit with the first of the semiconductor devices that shorts first one of the bit lineS to ground in response to signal on a second of the word lines when the first semiconductor device is conductive; c. a regenerative cell associated with each of the bit lines and each having: i. a first conductive device which is rendered conductive or nonconductive to store data by the changing of the charge level in one of its interelectrode capacitances; ii. a second semiconductor device which couples said interelectrode capacitance to one of the bit lines for charging and discharging said interelectrode capacitance in the restoration cell in response to signals on a third of the word lines; and iii. a third semiconductor device which forms a series circuit with the first of the semiconductor devices of the regenerative cell that shorts said one of the bit lines to ground in response to signals on a fourth of the word lines when the first of the semiconductor devices in the regenerative cell is conductive; and d. restoration means for periodically transferring data between said storage cells and said restoration cells to restore the data in the storage cells.

Claim 7

A word-oriented matrix of stored-charge memory cells comprising: a. a plurality of word and bit lines; b. a plurality of stored charge storage cells each having i. a first semiconductor device which is rendered conductive or nonconductive to store data by the changing of the charge level on one of its interelectrode capacitances; ii. a second semiconductor device which couples said one of the interelectrode capacitances to one of the bit lines for charging and discharging said interelectrode capacitance in response to signals on a first of the word lines; iii. a third semiconductor device which forms a series circuit with the first of the semiconductor devices that shorts first one of the bit lineS to ground in response to signal on a second of the word lines when the first semiconductor device is conductive; c. a regenerative cell associated with each of the bit lines and each having: i. a first conductive device which is rendered conductive or nonconductive to store data by the changing of the charge level in one of its interelectrode capacitances; ii. a second semiconductor device which couples said interelectrode capacitance to one of the bit lines for charging and discharging said interelectrode capacitance in the restoration cell in response to signals on a third of the word lines; and iii. a third semiconductor device which forms a series circuit with the first of the semiconductor devices of the regenerative cell that shorts said one of the bit lines to ground in response to signals on a fourth of the word lines when the first of the semiconductor devices in the regenerative cell is conductive; and d. restoration means for periodically transferring data between said storage cells and said restoration cells to restore the data in the storage cells.

Claim 8

The word oriented matrix of claim 5 including: means coupled to the second and third word lines for rendering the third device of a storage cell and the second device of a regenerative cell conductive at the same time to transfer the data stored in the storage cell into the regeneration cell and means coupled to the first and the fourth lines for rendering the second device of a storage cell and the third device of a regenerative cell conductive at the same time to transfer the data placed in the storage cell back into the storage cell whereby data in the storage cells can be periodically restored.

Claim 9

The matrix of claim 6 wherein said devices are field effect transistors.