Patent US3646451A successfully refreshed from Google Patents.
US3646451A
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Timing extraction circuit using a recirculating delay generator
Assignee: AT&T Inc
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Filing: 1970-08-07
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Granted: 1972-02-29
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Expires: 1990-08-07
Abstract
Abstract A timing circuit generates the timing signal used in the regeneration of pulse code modulation signals by taking a previously regenerated signal and inserting pulses where they are missing from the original signal. The inserted pulses are created in a recirculating delay generator which is synchronized with the incoming data and whose outputs is inhibited by delaying the input pulses for various periods and applying them to the output gate of the generator so that an output pulse from the generator is available only when there is no input pulse. The output of the generator is then summed at the output gate of the circuit with the original signal, producing a continuous stream of timing pulses.
Inventors
- 👤 Stephen Davis Shoap
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:47
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0066
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
345 words
A circuit for inserting pulses in the empty time slots of an incoming digital pulse train, said pulse train being characterized by a particular pulse repetition rate and said circuit comprising: first gating means having first and second inputs for producing an output pulse upon the occurrence of a pulse on either of said inputs, means for applying the input signal delayed for a first interval equal to a fraction of a pulse period to said first input, means for applying the output of a gated recirculating pulse generator to the second input of said gating means; said recirculating pulse generator comprising a second gating means having two inputs for producing a negative output pulse upon the occurrence of a positive pulse on either of said inputs, means for applying the input signal delayed for the aforementioned first interval to one input of said second gating means, means for applying the output of said second gating means delayed for a full pulse period to one input of a third gating means having a plurality of inputs, said third gating means producing a positive pulse output on the simultaneous absence of a positive pulse on all of said plurality of inputs, means for applying the output of said third gating means to the second input of said second gating means, thereby creating a recirculating pulse generator; means for applying said input pulse train to a second input of said third gAting means, means for applying the input signal delayed for the aforementioned first interval to a third input of said third gating means, means for applying the input signal delayed for increasing intervals up to a full pulse period to the other inputs of said third gating means, means for applying the output of said third gating means to the second input of said first gating means, the various delay intervals and multiples thereof being so related that said third means applies a pulse to the input of said first means only in the absence of a pulse at the other input of said first means.
Claim 2
Dependent Claim
345 words
A circuit for inserting pulses in the empty time slots of an incoming digital pulse train, said pulse train being characterized by a particular pulse repetition rate and said circuit comprising: first gating means having first and second inputs for producing an output pulse upon the occurrence of a pulse on either of said inputs, means for applying the input signal delayed for a first interval equal to a fraction of a pulse period to said first input, means for applying the output of a gated recirculating pulse generator to the second input of said gating means; said recirculating pulse generator comprising a second gating means having two inputs for producing a negative output pulse upon the occurrence of a positive pulse on either of said inputs, means for applying the input signal delayed for the aforementioned first interval to one input of said second gating means, means for applying the output of said second gating means delayed for a full pulse period to one input of a third gating means having a plurality of inputs, said third gating means producing a positive pulse output on the simultaneous absence of a positive pulse on all of said plurality of inputs, means for applying the output of said third gating means to the second input of said second gating means, thereby creating a recirculating pulse generator; means for applying said input pulse train to a second input of said third gAting means, means for applying the input signal delayed for the aforementioned first interval to a third input of said third gating means, means for applying the input signal delayed for increasing intervals up to a full pulse period to the other inputs of said third gating means, means for applying the output of said third gating means to the second input of said first gating means, the various delay intervals and multiples thereof being so related that said third means applies a pulse to the input of said first means only in the absence of a pulse at the other input of said first means.
Claim 3
Dependent Claim
181 words
A timing circuit for generating timing information from input pulse coded data, said circuit having an input and an output and comprising: a delay recirculator circuit comprising a two-input NOR gate, means for delaying the input pulse coded data for a first period and applying the delayed data to one input of said two-input gate, a multiinput NOR gate whose output is the output of said recirculator circuit, means for delaying the output of said two-input NOR gate for a second period equivalent to the basic pulse repetition rate of the input pulse coded data and applying the delayed output to one input of said multiinput NOR gate, and means for applying the output of said multiinput NOR gate to the other input of said two-input NOR gate; inhibiting means for blocking the output of said recirculator circuit whenever a pulse is present at the input to the timing circuit; and gating means for combining the output of said recirculator circuit with the input pulse coded data to produce a continuous series of pulses at the output of said timing circuit.
Claim 4
Dependent Claim
181 words
A timing circuit for generating timing information from input pulse coded data, said circuit having an input and an output and comprising: a delay recirculator circuit comprising a two-input NOR gate, means for delaying the input pulse coded data for a first period and applying the delayed data to one input of said two-input gate, a multiinput NOR gate whose output is the output of said recirculator circuit, means for delaying the output of said two-input NOR gate for a second period equivalent to the basic pulse repetition rate of the input pulse coded data and applying the delayed output to one input of said multiinput NOR gate, and means for applying the output of said multiinput NOR gate to the other input of said two-input NOR gate; inhibiting means for blocking the output of said recirculator circuit whenever a pulse is present at the input to the timing circuit; and gating means for combining the output of said recirculator circuit with the input pulse coded data to produce a continuous series of pulses at the output of said timing circuit.
Claim 5
Dependent Claim
119 words
A circuit as claimed in claim 2 wherein said inhibiting means comprises a plurality of delay means for delaying the input pulse coded data for discrete periods, the periods being chosen so that there will be an output from at least one of said plurality of delay means over a period equivalent to the basic pulse repetition rate whenever a data pulse is present at the input to the circuit, and means for applying the outputs of said plurality of delay means and the input pulse coded data to separate inputs of said multiinput NOR gate of said recirculator whereby the output of the recirculator is inhibited when a pulse is present at the input of said timing circuit.
Claim 6
Dependent Claim
136 words
A timing circuit as claimed in claim 2 in combination with a rectifier-regenerator whose input is the input of a regenerative repeater and whose output is both the output of said repeater and the input of said timing circuit, a voltage-controlled oscillator, a phase comparator, means for comparing the phase of the output of said timing circuit with the output of said voltage-controlled oscillator in said phase comparator, means for amplifying and filtering the output of said phase comparator, and applying the amplified and filtered signal to the control input of said voltage-controlled oscillator, thereby causing the output of said voltage-controlled oscillator to change frequency in response to said phase comparison, and means for applying the output of said voltage-controlled oscillator to a timing input of said rectifier-regenerator, thereby determining the sampling time in the rectifier-regenerator.
Claim 7
Dependent Claim
63 words
A timing circuit as claimed in claim 2 in combination with a rectifier-regenerator whose input is the input of a regenerative repeater and whose output is both the output of said repeater and the input of said timing circuit, means for applying the output of said timing circuit to a timing input of said rectifier-regenerator, thereby determining the sampling time in the rectifier-regenerator.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-02-28 | 1975-08-30 | 1976-02-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-02-28 | 1979-08-30 | 1980-02-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-02-28 | 1983-08-30 | 1984-02-29 | $7700.00 | Window Closed / Lapsed |