Patent US3646364A successfully refreshed from Google Patents.
US3646364A
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Circuit for reducing switching transients in fet operated gates
Assignee: AT&T Inc
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Filing: 1969-11-17
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Granted: 1972-02-29
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Expires: 1989-11-17
Abstract
Abstract An FET analog gate includes two equal-valued resistors, one in the source path and one in the drain path of the FET, and a differential amplifier, one input connected to the FET source terminal and the other input connected to the FET drain terminal.
Inventors
- 👤 William Kaminski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:25
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/02; H03F; H03F3/00; H03F3/38; H03F3/387; H03F3/393
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
US3363166A
Cited
US3469173A
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US3397353A
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US3522519A
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US3458799A
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US3510684A
Cited
US3495097A
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US3521087A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-02-28 | 1975-08-30 | 1976-02-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-02-28 | 1979-08-30 | 1980-02-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-02-28 | 1983-08-30 | 1984-02-29 | $7700.00 | Window Closed / Lapsed |