Information transmission systems

Claim 1

An information-communicating system for receiving and synchronizing information data transmitted from one location to a remote location, and including in combination: a. receiving-addressing means having an N number of inputs corresponding to an N number of input frequencies, an n number of input frequencies transmitted in a preselected sequence such that the occurrence of each specific frequency is within a predetermined time period, and wherein n is less than N, said receiving-addressing means also having a data input, said combination of n number of input frequencies comprising an address for n particular locations and defining the length of a word for a given function, said word comprising n number of bits appearing on n number of outputs from said receivingaddressing means, said receiving-addressing means having an end-of-bit output pulse which is produced at the end of each predetermined time period and an end-of-word output pulse which is produced at the end of the nth predetermined time period, b. data control means having a plurality of inputs corresponding to an equal plurality of data frequencies which produce a first and second control data output, said first control data output electrically connected to said data input of said receivingaddressing means and being in either a first or a second binary condition dependent upon the presence or absence of selected ones of said plurality of data frequencies, the presence of said first binary condition on said data input and the simultaneous occurrence of one of said n number of address frequencies causing said first binary condition to be produced on the corresponding one of said n number of outputs of said receiving-addressing means, and the presence of said second binary condition on said data input and the simultaneous occurrence of one of said n number of address frequencies causing said second binary condition to be produced on the corresponding one of said n number of outputs of said receiving-addressing means, c. a false data inhibiting means having a first and a second input electrically connected to said receiving-addresssing means to respectively receive said end-of-bit output pulse and said end-of-word output pulse, said false data inhibiting means having a third input electrically connected to said control data output of said data control means and being in a first binary condition wheneveR all of said plurality of data frequencies are present on said plurality of inputs to said data control means and also being in said binary condition whenever none of said plurality of data frequencies are present on said plurality of inputs to said data control means, said third input to said false data inhibiting means being in a second binary condition in all other instances, said false data inhibiting means also having a registry control output being in said first binary condition only at the end of said nth predetermined time period and in the presence of said first binary condition on said third input to said false data inhibiting means, said registry control output being in said second binary condition in all other instances, said first and second inputs to said false data inhibiting means employed to ensure the presence of said first binary condition on said registry control output only at the end of said nth predetermined time period, said second input to said false data inhibiting means employed to recycle said false data inhibiting means at the end of a word, d. storage means having n number of inputs and an n number of outputs, said n number of inputs of said storage means electrically connected to said receiving-addressing means to receive said n number of outputs of said receiving-addressing means, said n number of inputs to said storage means being initially temporarily stored in a sequential manner, said storage means also electrically coupled to said registry control output from said false data inhibiting means, said n outputs of said storage means simultaneously appearing as n number of bits only in the presence of said second binary condition on said registry control output of said false data inhibiting means, thereby providing said synchronizing of said information data.