Correction circuit for converters

Claim 2

An error correction circuit for an analog-to-digital signal converter, comprising: an analog-to-digital converter including input circuit means for receiving an analog input signal to be converted, and counterand-storage circuit means for storing said analog input signal as a preliminary digital signal; said input circuit means including means for generating error signals representing the analog difference between said analog input signal and said stored preliminary digital signal; error sample-and-hold means connected to said means for generating error signals included in said input circuit means for receiving and holding said error signals generated therefrom; analog error to digital error conversion means for receiving said error signals from said error sample-and-hold means and converting said signals to a digital error signal; and said counter-and-storage circuit means connected to said analog error to digital error conversion means for receiving said digital error signals and correcting said preliminary digital signal stored therein, thus converting said preliminary signal to a corrected digital output signal.

Claim 3

An error correction circuit for an analog-to-digital converter as claimed in claim 1, additionally comprising: said input circuit means including means for generating a reference signal indicative of said preliminary digital signal; reference sample-and-hold means connected to said means for generating a reference signal included in said input circuit means for receiving and holding said reference signal generated therefrom; said analog error to digital error conversion means connected to said reference sample-and-hold means for comparing said error signals from said error sample-and-hold means with said reference signals from said reference sample-and-hold means.

Claim 4

An error correction circuit for an analog-to-digital converter as claimed in claim 1, additionally comprising: said input circuit means including means for generating a reference signal indicative of said preliminary digital signal; reference sample-and-hold means connected to said means for generating a reference signal included in said input circuit means for receiving and holding said reference signal generated therefrom; said analog error to digital error conversion means connected to said reference sample-and-hold means for comparing said error signals from said error sample-and-hold means with said reference signals from said reference sample-and-hold means.

Claim 5

An error correction circuit for an analog-to-digital converter as claimed in claim 1, additionally comprising: sample-and-hold means for sampling said analog input signal to be converted and holding said signal for receipt by input circuit means included in said analog-to-digital converter; said sample-and-hold means including a reference potential and switching means for connecting said sample-and-hold means and thus said input circuit means of said analog-to-digital converter alternately to said analog input signal and then to said reference potential; said error sample-and-hold means connected to said means for generating error signals including an error sample-and-hold circuit, a summing circuit, means connecting said error sample-and-hold circuit between said means for generating error signals included in said input circuit means and said summing circuit, and means connecting said means for generating error signals included in said input circuit means directly to said summing circuit; said summing circuit having an output connected to said analog error to digital error conversion means; and means controlling said switching means for connecting said sample-and-hold means to said reference potential thus generating an offset error signal which is applied to said summing circuit through said input circuit means and said means connecting said means for generating error signals included in said input circuit means directly to said summing circuit; said summing circuit generating a corrected error signal fOrmed from the difference between said offset error signal and said error signals stored within said error sample-and-hold means which is applied over said summing circuit output to said analog error to digital error conversion means.

Claim 6

An error correction circuit for an analog-to-digital converter as claimed in claim 3, additionally comprising: polarity detect means connected to said summing circuit output for detecting the polarity of said corrected error signal and generating an output response thereto, means connecting said output response from said polarity detect means to said summing circuit for reversing said polarity of said corrected error signal where necessary; and means connecting said output response from said polarity detect means to said counter-and-storage circuit means for controlling the count direction of said digital error signal from said analog error to digital error conversion means as said digital error signal is applied to said counter-and-storage circuit means.

Claim 7

An error correction circuit for an analog-to-digital converter, comprising: input signal sample-and-hold means connected to receive an analog input signal to be converted to a digital output signal; said input sample-and-hold means including a reference potential and input switching means for connecting said input sample-and-hold means to said reference potential; an analog-to-digital converter including analog input circuit means for receiving said analog input signal, and counter and digital storage circuit means for storing said analog input signal as a preliminary digital signal; said analog input circuit means including means for generating an error signal representing the analog difference between said analog input signal and said stored preliminary digital signal and means for generating a reference signal representing the magnitude levels of said analog input signal; error sample-and-hold means connected to said means for generating an error signal for receiving and holding said error signal; summing circuit means connected to said means for generating an error signal for receiving said error signal therefrom and connected to said error sample-and-hold means for receiving said error signal held therein; reference sample-and-hold means connected to said means for generating a reference signal for receiving and holding said reference signal; error analog-to-digital conversion means connected to receive said error signal from said summing circuit means and to receive said reference signal held in said reference sample-and-hold means having an output connected to said counter and digital storage circuit means; means controlling said input-switching means within said input sample-and-hold means for connecting said input sample-and-hold means to said reference potential thus generating an offset error signal as said error signal; said means controlling said input-switching means controlling said error sample-and-hold means for placing said means in a hold position thereby applying said error signal held therein to said summing circuit as said offset error signal is applied thereto for generating a corrected error signal free of said offset error signal therefrom; and said means controlling said input-switching means also controlling said reference sample-and-hold means for placing said means in a hold position thereby applying said reference signal held therein to said error analog-to-digital conversion means to generate a digital signal representing said corrected error signal for application to said counter and digital storage circuit to correct said stored preliminary digital signal; whereby a corrected digital signal equaling said analog input signal is produced.

Claim 8

An error correction circuit for an analog-to-digital converter, comprising: input signal sample-and-hold means connected to receive an analog input signal to be converted to a digital output signal; said input sample-and-hold means including a reference potential and input switching means for connecting said input sample-and-hold means to said reference potential; an analog-to-digital converter including analog input circuit means for receiving said analog input signal, and counter and digital storage circuit means for storing said analog input signal as a preliminary digital signal; said analog input circuit means including means for generating an error signal representing the analog difference between said analog input signal and said stored preliminary digital signal and means for generating a reference signal representing the magnitude levels of said analog input signal; error sample-and-hold means connected to said means for generating an error signal for receiving and holding said error signal; summing circuit means connected to said means for generating an error signal for receiving said error signal therefrom and connected to said error sample-and-hold means for receiving said error signal held therein; reference sample-and-hold means connected to said means for generating a reference signal for receiving and holding said reference signal; error analog-to-digital conversion means connected to receive said error signal from said summing circuit means and to receive said reference signal held in said reference sample-and-hold means having an output connected to said counter and digital storage circuit means; means controlling said input-switching means within said input sample-and-hold means for connecting said input sample-and-hold means to said reference potential thus generating an offset error signal as said error signal; said means controlling said input-switching means controlling said error sample-and-hold means for placing said means in a hold position thereby applying said error signal held therein to said summing circuit as said offset error signal is applied thereto for generating a corrected error signal free of said offset error signal therefrom; and said means controlling said input-switching means also controlling said reference sample-and-hold means for placing said means in a hold position thereby applying said reference signal held therein to said error analog-to-digital conversion means to generate a digital signal representing said corrected error signal for application to said counter and digital storage circuit to correct said stored preliminary digital signal; whereby a corrected digital signal equaling said analog input signal is produced.

Claim 9

An error correction circuit for an analog-to-digital converter as claimed in claim 5, additionally comprising: polarity detect means connected to said summing circuit means for detecting the polarity of said corrected error signal proDuced thereby; said summing circuit including switching means controlled by said polarity detect means for switching said error signal and said offset error signal applied thereto in response to said polarity of said corrected error signal generated therefrom; and said polarity detect means connected to said counter and digital storage circuit means for determining the direction of count of said digital signal representing said corrected error signal during the correction of said preliminary digital signal stored therein.

Claim 10

An error correction circuit for an analog-to-digital converter as claimed in claim 5, wherein said summing circuit means comprises: input terminal means for receiving said error signal and said offset error signal; amplifier means including first and second input terminals and an output terminal; first summing means connected to said input terminal means for summing said error and said offset error signals, second summing means connected to said input terminal means for summing said error and said offset error signals; a source of reference potential; first switching means connecting said first summing means to said first amplifier input terminal and connecting said second amplifier input terminal to said source of reference potential; and second switching means connecting said second summing means to said second amplifier input terminal and connecting said first amplifier input terminal to said source of reference potential, thereby controlling the signal polarity of said corrected error signal at said output terminal.

Claim 11

An error correction circuit for an analog-to-digital converter as claimed in claim 7, additionally comprising polarity detect circuit means including: amplifier means having an input for receiving said corrected error signal and an output for an output signal; limiting means connected to said output to limit said output signal; flip-flop means having first and second outputs and an input connected to receive said amplifier output signal and arranged to change state when said output signal drops below a predetermined level; and said first and second outputs connected respectively to said first and second switching means within said summing circuit for controlling said first and second switching means and said polarity of said corrected error signal.

Claim 12

An error correction circuit for an analog-to-digital converter as claimed in claim 5, wherein said sample-and-hold means each comprise: an input terminal for receiving one of said signals to be sampled and held; a summing junction; a source of reference potential; an amplifier having an input terminal connected to said summing junction, an input terminal connected to said source of reference potential, and an output terminal; memory means connected to said amplifier output terminal; first switching means connecting said input terminal to said summing junction and connecting said memory means to said source of reference potential for sampling one of said signals; and second switching means connecting said input terminal to said source of reference potential and connecting said memory means to said summing junction for holding one of said sampled signals and providing an output signal at said output terminal equaling said held signal.

Claim 13

An error correction circuit for an analog-to-digital converter as claimed in claim 9, wherein said sample-and-hold means include said error sample-and-hold means and said reference sample-and-hold means, and said first and second switching means include pairs of field effect transistors.

Claim 14

An error correction circuit for an analog-to-digital converter as claimed in claim 9, wherein said sample-and-hold means includes said input sample-and-hold means and additionally comprising: resistance means; said input switching for connecting said input sample-and-hold means to said reference potential connecting said resistance meAns between said source of reference potential and said summing junction; and said input switching means and said first and second switching means including field effect transistors.