US3641331A — Apparatus for performing arithmetic operations on…

Claim 1

Independent Claim 204 words

A decimal multiplying system for multiplying a multiplicand by successive digits of a multiplier each number represented by a plurality of decimal digits, said system comprising: memory means for storing a number of separate decimal digits representing said multiples of the multiplicand, said number of nonzero multiples generated and stored being equal to half of the total number of decimal digit symbols employed by said system; an adder including first and second terminals; an accumulator register for holding an accumulated partial product, said register being coupled to said first terminal of said adder; logic means coupled to said memory means and to said second terminal of said adder; multiplier decoder means coupled to said memory means for conditioning said memory means for selecting an appropriate one of said stored multiples in accordance with the sum of digit value of said multiplier digit and previous multiplier digit and said decoder means being coupled to said logic means for conditioning said means for selectively performing a single operation on each selected multiple in accordance with said sum for generation of all of the possible multiples required which are thereafter applied to said first terminal of said adder for addition to the contents of said accumulator register.

Claim 2

Dependent Claim 204 words

A decimal multiplying system for multiplying a multiplicand by successive digits of a multiplier each number represented by a plurality of decimal digits, said system comprising: memory means for storing a number of separate decimal digits representing said multiples of the multiplicand, said number of nonzero multiples generated and stored being equal to half of the total number of decimal digit symbols employed by said system; an adder including first and second terminals; an accumulator register for holding an accumulated partial product, said register being coupled to said first terminal of said adder; logic means coupled to said memory means and to said second terminal of said adder; multiplier decoder means coupled to said memory means for conditioning said memory means for selecting an appropriate one of said stored multiples in accordance with the sum of digit value of said multiplier digit and previous multiplier digit and said decoder means being coupled to said logic means for conditioning said means for selectively performing a single operation on each selected multiple in accordance with said sum for generation of all of the possible multiples required which are thereafter applied to said first terminal of said adder for addition to the contents of said accumulator register.

Claim 3

Dependent Claim 44 words

A decimal multiplying system according to claim 1 wherein said total number equals 10 and the decimal digits representing the multiplicand multiples 1, 2, 3, 4, and 5 are the only of said multiples initially generated and stored in said memory means for selection.

Claim 4

Dependent Claim 52 words

A decimal multiplying system according to claim 1 wherein said multiplier decoder means upon sensing a predetermined digit value for said previous multiplier digit representing a carry is operative to condition said memory means for selecting the next successive multiple of said multiplicand for application to said first input of said adder.

Claim 5

Dependent Claim 15 words

The system according to claim 3 wherein said predetermined digit value is greater than 5.

Claim 6

Dependent Claim 111 words

The system according to claim 1 wherein said logic means includes logic gating means and complementor means, each being connected to said memory means to receive in parallel said separate decimal digits representing said multiples from said memory means, each of said last-mentioned means conditioned by said decoding means upon the sensing of a predetermined digit value for the sum of said multiplier digit and said previous multiplier digit representative of a Carry, to selectively apply the multiple selected by said multiplier digit either directly or complemented to said first terminal of said adder to generate all of the possible multiples to be added to said contents of said accumulator register.

Claim 7

Dependent Claim 47 words

The system according to claim 5 wherein said complementer means performs a 10''s complement operation on said selected multiple when said predetermined digit value of said sum lies between 6 and 10 whereafter said decoder means is operative to generate a carry for the next multiplier digit.

Claim 8

Dependent Claim 45 words

The system according to claim 5 wherein said complementor means performs a 9''s complement operation on said selected multiple and said decoder means introduces a forced carry-in signal into said adder when said predetermined digit value is greater than 5, completing the 10''s complement operation.

Claim 9

Dependent Claim 303 words

A multiplier for a data processing system, the combination comprising: addressable memory means including address register means and a number of multiplicand multiple registers for storing different selected multiples of the multiplicand in binary coded decimal code, said number of nonzero multiples stored being equal to half the total number of digit symbols employed in said system and said multiples capable of being grouped into a direct multiple set and a complement multiple set derivable from said direct set in which the multiples (M-1) of both sets are mutually exclusive; an adder; multiplier register means for storing successive decimal digits of a multiplier, said register means being coupled to said address register means for addressing individual ones of registers; first logic gating means coupled to said memory means and to said adder and when enabled for directly transferring said signal representations of said multiples of said direct set from said addressed memory registers; second logic gating means coupled to said memory means and to said adder in parallel with said first logic means, said second logic means when enabled for transferring the complement of said signal representations of said multiples of said complement set from said addressed memory registers; and decoding means coupled to said multiplier register means and to said address register means, said decoding means responsive to the value of the sum of each of the successive multiplier digits and a possible carry from a previous multiplier digit to condition said addressing means to select a predetermined one of said multiples, and said decoding means being connected to selectively enable said first and second logic means in accordance with said sum to selectively transfer said signal representation of said selected multiple directly and complemented through said first and second gating means respectively for generation of all possible multiples of said multiplicand.

Claim 10

Dependent Claim 303 words

A multiplier for a data processing system, the combination comprising: addressable memory means including address register means and a number of multiplicand multiple registers for storing different selected multiples of the multiplicand in binary coded decimal code, said number of nonzero multiples stored being equal to half the total number of digit symbols employed in said system and said multiples capable of being grouped into a direct multiple set and a complement multiple set derivable from said direct set in which the multiples (M-1) of both sets are mutually exclusive; an adder; multiplier register means for storing successive decimal digits of a multiplier, said register means being coupled to said address register means for addressing individual ones of registers; first logic gating means coupled to said memory means and to said adder and when enabled for directly transferring said signal representations of said multiples of said direct set from said addressed memory registers; second logic gating means coupled to said memory means and to said adder in parallel with said first logic means, said second logic means when enabled for transferring the complement of said signal representations of said multiples of said complement set from said addressed memory registers; and decoding means coupled to said multiplier register means and to said address register means, said decoding means responsive to the value of the sum of each of the successive multiplier digits and a possible carry from a previous multiplier digit to condition said addressing means to select a predetermined one of said multiples, and said decoding means being connected to selectively enable said first and second logic means in accordance with said sum to selectively transfer said signal representation of said selected multiple directly and complemented through said first and second gating means respectively for generation of all possible multiples of said multiplicand.

Claim 11

Dependent Claim 36 words

The multiplier of claim 8 wherein said decoding means in response to a predetermined sum conditions said address register means to address the multiple register storing the next highest multiple register for transfer to said adder.

Claim 12

Dependent Claim 39 words

The multiplier of claim 8 wherein said decoding means is responsive to digit values between 0 and 5 and 6 and 10 respectively to transfer the signal representation of said multiple through said first and second logic gating means.

Claim 13

Independent Claim 421 words

A system for performing arithmetic calculations with first and second operands representative of binary coded multidigit numbers with each digit having at least four bits, said calculations being performed in a mode of operation wherein a predetermined number of multiples of said first operand are initially generated and stored with each of all of the possible multiples required for the performance of a particular arithmetic operation involving said operands being subsequently generated from the previously stored multiples, said system comprising: addressable memory storage means having an input and an output, said stoRage means including a plurality of multiple registers, each for storing a different one of said multiples of said first operand; an arithmetic device for adding two number signals applied to first and second terminals thereof; logic means coupled to said memory means and to said device, said logic means conditioned for performing a single operation of selectively transferring the multiple at said output directly or in complement from to said device; an accumulator register connected to said second terminal for storing the intermediate results of an arithmetic operation; multiplier register means for storing each of the successive digits of said second operand, said register means being coupled to said input of said storage means; microprogrammed control sequencing means connected to be responsive to an op code of an instruction for specifying the type of arithmetic operation to be performed, to produce first sets of control signals for conditioning said system to generate from said first operand said predetermined number of said different selected multiples and store said multiples in said storage means, said predetermined number of nonzero multiples stored being equal to half the total range of multiples capable of being signaled by the sum of largest multiplier digit and a carry from the previous multiplier digit and, said microprogrammed control means operative during the processing of each multiplier digit during said performance of said arithmetic operation to produce second sets of control signals to produce all possible multiples for said arithmetic device involving said digit by conditioning said logic means to perform said single operation upon the contents of each of the addressed operand multiples in accordance with the value of each of said multiplier digits and said carry whereby said arithmetic device adds each of said addressed operand multiples applied by said logic means to said first terminal to the contents of said accumulator register whereafter a chosen number of cycles of said second sets of control signals, the final results of said arithmetic operation are obtained.

Claim 14

Independent Claim 421 words

A system for performing arithmetic calculations with first and second operands representative of binary coded multidigit numbers with each digit having at least four bits, said calculations being performed in a mode of operation wherein a predetermined number of multiples of said first operand are initially generated and stored with each of all of the possible multiples required for the performance of a particular arithmetic operation involving said operands being subsequently generated from the previously stored multiples, said system comprising: addressable memory storage means having an input and an output, said stoRage means including a plurality of multiple registers, each for storing a different one of said multiples of said first operand; an arithmetic device for adding two number signals applied to first and second terminals thereof; logic means coupled to said memory means and to said device, said logic means conditioned for performing a single operation of selectively transferring the multiple at said output directly or in complement from to said device; an accumulator register connected to said second terminal for storing the intermediate results of an arithmetic operation; multiplier register means for storing each of the successive digits of said second operand, said register means being coupled to said input of said storage means; microprogrammed control sequencing means connected to be responsive to an op code of an instruction for specifying the type of arithmetic operation to be performed, to produce first sets of control signals for conditioning said system to generate from said first operand said predetermined number of said different selected multiples and store said multiples in said storage means, said predetermined number of nonzero multiples stored being equal to half the total range of multiples capable of being signaled by the sum of largest multiplier digit and a carry from the previous multiplier digit and, said microprogrammed control means operative during the processing of each multiplier digit during said performance of said arithmetic operation to produce second sets of control signals to produce all possible multiples for said arithmetic device involving said digit by conditioning said logic means to perform said single operation upon the contents of each of the addressed operand multiples in accordance with the value of each of said multiplier digits and said carry whereby said arithmetic device adds each of said addressed operand multiples applied by said logic means to said first terminal to the contents of said accumulator register whereafter a chosen number of cycles of said second sets of control signals, the final results of said arithmetic operation are obtained.

Claim 15

Dependent Claim 379 words

A multiplier which operates by additions of multiplicand multiples from a partial product, each multiple represented by digits in a decimal code, comprising: an addressable memory including a plurality of multiple storage locations for storing zero, first, second, third, fourth and fifth multiples generated from the multiplicand and being equal to the multiplicand multiplied by 0, 1, 2, 3, 4 and 5, said memory further including an address register for addressing each of said storage locations for readout of the contents thereof; first and second shiftable accumulator registers, each having a high-order end and a low-order end for initially holding the multiplier and for receiving the digits of the final product and accumulated partial product respectively during the multiplication operation, said low-order end of said first accumulator register being coupled to said address register; shift means coupled to said accumulator registers to enter a digit of the final product at the high end of said second accumulator register and to shift the contents of said first and second registers by one digit position whereby the digit shifting ut the low-order end of said first accumulator registers enters the high-order end of said second register; an adder means having first and second terminals; means connecting said first terminal to said second accumulator register; logic means connecting said memory to said second terminal; decoder and storage means coupled to said low-order end of said first accumulator register and being operative to generate first and second output signals respectively when the sum of said multiplier digit and carry generated by a previous digit has a value less than or equal to 5 and when the sum of said multiplier digit and previous carry has a value greater than 5; and, microprogramming contrOl means coupled to said addressable memory and to said accumulator registers and being operative during the processing of each multiplier digit to condition said first register to apply successive digits as an address to said address register for selecting each multiple in accordance with the sum of said multiplier digit and carry when generated by a previous multiplier digit and to condition said logic means to transfer said multiple directly or complemented in accordance with said first and second output signals for addition to contents of said second accumulator register.

Claim 16

Dependent Claim 379 words

A multiplier which operates by additions of multiplicand multiples from a partial product, each multiple represented by digits in a decimal code, comprising: an addressable memory including a plurality of multiple storage locations for storing zero, first, second, third, fourth and fifth multiples generated from the multiplicand and being equal to the multiplicand multiplied by 0, 1, 2, 3, 4 and 5, said memory further including an address register for addressing each of said storage locations for readout of the contents thereof; first and second shiftable accumulator registers, each having a high-order end and a low-order end for initially holding the multiplier and for receiving the digits of the final product and accumulated partial product respectively during the multiplication operation, said low-order end of said first accumulator register being coupled to said address register; shift means coupled to said accumulator registers to enter a digit of the final product at the high end of said second accumulator register and to shift the contents of said first and second registers by one digit position whereby the digit shifting ut the low-order end of said first accumulator registers enters the high-order end of said second register; an adder means having first and second terminals; means connecting said first terminal to said second accumulator register; logic means connecting said memory to said second terminal; decoder and storage means coupled to said low-order end of said first accumulator register and being operative to generate first and second output signals respectively when the sum of said multiplier digit and carry generated by a previous digit has a value less than or equal to 5 and when the sum of said multiplier digit and previous carry has a value greater than 5; and, microprogramming contrOl means coupled to said addressable memory and to said accumulator registers and being operative during the processing of each multiplier digit to condition said first register to apply successive digits as an address to said address register for selecting each multiple in accordance with the sum of said multiplier digit and carry when generated by a previous multiplier digit and to condition said logic means to transfer said multiple directly or complemented in accordance with said first and second output signals for addition to contents of said second accumulator register.

Claim 17

Dependent Claim 186 words

An electronic calculator comprising: an addressable memory storage means including a plurality of register locations for storing a chosen number of different multiples of a multiplicand, said number exclusive of zero being equal to half of the total number of multiplier digit symbols employed by said calculator; an adder for adding each received signal representation of each selected multiple to a partial accumulated sum; logic gating means coupled to said memory means and to said adder for directly transferring each said signal representation of said multiple a multiplicand received from said storage means to said adder; logic translation means coupled to said memory means and to said adder for transferring a complement signal representation of said multiple received from said storage means to said adder; and decoder means being operative in response to each successive multiplier digit received to selectively condition said logic gating means and said translation means to generate all of said multiples required by the total number of digit symbols through either a direct transfer or a complementing of a prestored multiple selected in accordance with the value of each successive multiplier digit.

Claim 18

Dependent Claim 186 words

An electronic calculator comprising: an addressable memory storage means including a plurality of register locations for storing a chosen number of different multiples of a multiplicand, said number exclusive of zero being equal to half of the total number of multiplier digit symbols employed by said calculator; an adder for adding each received signal representation of each selected multiple to a partial accumulated sum; logic gating means coupled to said memory means and to said adder for directly transferring each said signal representation of said multiple a multiplicand received from said storage means to said adder; logic translation means coupled to said memory means and to said adder for transferring a complement signal representation of said multiple received from said storage means to said adder; and decoder means being operative in response to each successive multiplier digit received to selectively condition said logic gating means and said translation means to generate all of said multiples required by the total number of digit symbols through either a direct transfer or a complementing of a prestored multiple selected in accordance with the value of each successive multiplier digit.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1975-02-07	1975-08-09	1976-02-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1979-02-07	1979-08-09	1980-02-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1983-02-07	1983-08-09	1984-02-08	$7700.00	Window Closed / Lapsed

Apparatus for performing arithmetic operations on numbers using a multiple generating and storage technique

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