Bypass control system for high-voltage dc converter using semiconductor control rectifiers

Claim 2

In a converter constructed in the form of a multiphase graetz connection of silicon controlled rectifiers including a converter switch for connecting said converter to an AC bus, and a bypass switch, the improvement comprising means for bypassing said converter exclusive of a bypass valve, wherein a bypass pair of said silicon controlled rectifiers is established instead of bypass valves including a bypass control system for simultaneously firing two arms of said graetz connection in series in one phase of said converter wherein said system has a means for closing said bypass switch only when said converter switch is open.

Claim 3

In a converter constructed in the form of a multi-phase gate connection in which respective arms are constituted by sEmiconductor controlled rectifiers serving as valve elements, a bypass control system comprising automatic pulse phase shifter circuits for controlling the delay angle of the valves in the respective arms, a firing circuit for firing each valve by the use of the output of said phase shifter circuits, a bypass instruction circuit for providing an instruction to establish a bypass pair by simultaneously firing two arms in series in one phase, a memory circuit for memorizing that one of said phase shifter circuits which first provides an output when an output is provided by said instruction circuit, a block instruction circuit for interrupting the operation of said phase-shifter circuit when an output is provided by said memory circuit, and a pulse generating circuit for generating a firing pulse to fire the valves at a predetermined time after an output is provided by said memory circuit, and means responsive to the generation of an instruction for said bypass pair irrespective of trouble in the converter, for imparting the output of said pulse generating circuit to said firing circuit associated with a given arm in relation to the phase shifter circuit memorized by said memory circuit, and means responsive to the generation of an instruction based upon trouble in the converter, for preventing the output of said pulse generating circuit from being imparted to said firing circuit.

Claim 4

In a converter constructed in the form of a multi-phase gate connection in which respective arms are constituted by sEmiconductor controlled rectifiers serving as valve elements, a bypass control system comprising automatic pulse phase shifter circuits for controlling the delay angle of the valves in the respective arms, a firing circuit for firing each valve by the use of the output of said phase shifter circuits, a bypass instruction circuit for providing an instruction to establish a bypass pair by simultaneously firing two arms in series in one phase, a memory circuit for memorizing that one of said phase shifter circuits which first provides an output when an output is provided by said instruction circuit, a block instruction circuit for interrupting the operation of said phase-shifter circuit when an output is provided by said memory circuit, and a pulse generating circuit for generating a firing pulse to fire the valves at a predetermined time after an output is provided by said memory circuit, and means responsive to the generation of an instruction for said bypass pair irrespective of trouble in the converter, for imparting the output of said pulse generating circuit to said firing circuit associated with a given arm in relation to the phase shifter circuit memorized by said memory circuit, and means responsive to the generation of an instruction based upon trouble in the converter, for preventing the output of said pulse generating circuit from being imparted to said firing circuit.

Claim 5

A control system in accordance with claim 2, wherein said memory circuit includes a plurality of storage flip-flops respectively associated with each valve, each flip-flop being connected to the output of an associated AND gate, a common input of which is connected to the output of said bypass instruction circuit and another input of which is connected to the output of each respective automatic pulse phase shifter circuit.

Claim 6

A control system in accordance with claim 3, further including a plurality of AND gates respectively associated with each of said firing circuits, a common input of which is connected to said pulse generating circuit, and a respective input of which is connected to said flip-flops.

Claim 7

A control system in accordance with claim 4, further including an OR gate connected to each of the outputs of said flip-flops and whose output is connected to said block instructions circuit and wherein said pulse generating circuit includes a monostable multivibrator responsive to the output of said OR gate and an INHIBIT-AND gate connected to the output of said monostable multivibrator, the output of said INHIBIT-AND gate being connected to each of said AND gates associated with said firing circuits.

Claim 8

A control system in accordance with claim 5, wherein said preventing means includes a communication failure detector connected to the INHIBIT input of said INHIBIT-AND gate and to said bypass instruction circuit.

Claim 9

A control system in accordance with claim 2, wherein said control system further includes a current detector associated with each respective phase line of said multiphase connection and further including a control circuit, said control circuit including a first relay responsive to a converter starting signal for closing a pair of contacts associated across the voltage lines of said converter.

Claim 10

A control system in accordance with claim 7, further including a second relay, connected in series with one of the contacts of said first relay and a self-holding contact associated therewith for holding said relay operation in response to the closure of a stopping switch.

Claim 11

A control system in accordance with claim 8, further including a first set of relays connected in parallel across said voltage lines, a first auxiliary relay and a second auxiliary relay, said first relay effecting the operation of said converter in the bypass pair mode, the operation of said second auxiliary relay being responsive to the closure of the contacts of said first relay.