Patent US3636420A successfully refreshed from Google Patents.
US3636420A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low-capacitance planar varactor diode
Assignee: Texas Instruments Inc
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Filing: 1970-02-02
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Granted: 1972-01-18
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Expires: 1990-02-02
Abstract
Abstract A planar varactor diode for integrated circuit applications, especially at high frequencies, is disclosed. This diode has lowleakage currents, improved reversed bias characteristics, and reduced junction and MOS capacitance. The low-leakage currents are obtained by minimizing the surface perimeter of the device; the low-junction capacitance is obtained by reducing the junction area of the two active regions; and the reduced MOS capacitance is achieved by offsetting the anodic region underneath the anode contact.
Inventors
- 👤 George D Vendelin
- 👤 Roger R Webster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:15
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/64; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/031; Y10S148/05
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
203 words
A semiconductor device comprising in combination: a. a high-resistivity semiconductor substrate of one conductivity type; b. a low-resistivity first region of opposite conductivity type extending into said substrate from one surface of said substrate; c. a high-resistivity second region of said opposite conductivity type extending from said one surface at least partially into said first region and offset from the center of said first region; d. a low-resistivity third region extending into said second region from said one surface of said substrate and offset from the center of said second region to produce a PN-junction; e. an insulating layer upon said one surface of said substrate; f. a first metal contact overlying a portion of said insulating layer and extending through a first opening in said insulating layer over said second region; g. a second metal contact overlying a portion of said insulating layer and extending through a second opening in said insulating layer into contact with said first region, the portion of said insulating layer that is contiguous to said second metal contact being substantially positioned over said third region and said substrate, thereby substantially eliminating MOS capacity from said device and reducing the surface perimeter and shunting capacity of said device.
Claim 2
Dependent Claim
203 words
A semiconductor device comprising in combination: a. a high-resistivity semiconductor substrate of one conductivity type; b. a low-resistivity first region of opposite conductivity type extending into said substrate from one surface of said substrate; c. a high-resistivity second region of said opposite conductivity type extending from said one surface at least partially into said first region and offset from the center of said first region; d. a low-resistivity third region extending into said second region from said one surface of said substrate and offset from the center of said second region to produce a PN-junction; e. an insulating layer upon said one surface of said substrate; f. a first metal contact overlying a portion of said insulating layer and extending through a first opening in said insulating layer over said second region; g. a second metal contact overlying a portion of said insulating layer and extending through a second opening in said insulating layer into contact with said first region, the portion of said insulating layer that is contiguous to said second metal contact being substantially positioned over said third region and said substrate, thereby substantially eliminating MOS capacity from said device and reducing the surface perimeter and shunting capacity of said device.
Claim 3
Dependent Claim
19 words
A semiconductor device as set forth in claim 1 wherein said substrate has a resistivity greater than 1,500 ohm/centimeter.
Claim 4
Dependent Claim
104 words
The semiconductor device of claim 1 wherein said device is a diode and wherein: a. said one conductivity type is P-type and said opposite conductivity type is N-type; and wherein b. said first region is the cathode contact region of said diode and said first metal contact is the cathode contact of said diode; and wherein c. said third region is the anode contact region of said diode and said second metal contact is the anode contact of said diode; and wherein d. said second region is the cathode region of said diode which separates said cathode contact region from said anode contact region.
Claim 5
Dependent Claim
36 words
The semiconductor device of claim 1 wherein the relative position of said third region with respect to said first and second regions reduces the surface perimeter of said device thereby reducing leakage currents in said device.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-17 | 1975-07-19 | 1976-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-17 | 1979-07-19 | 1980-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-17 | 1983-07-19 | 1984-01-18 | $7700.00 | Window Closed / Lapsed |