US3634931A
Expired / Lapsed
US
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Method for manufacturing pressure sensitive semiconductor device
Assignee: Panasonic Holdings Corp
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Filing: 1969-12-09
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Granted: 1972-01-18
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Expires: 1989-12-09
Abstract
Abstract In a semiconductor device with a four-layer structure having the so-called thyristor characteristic, when the control electrode for controlling its breakover voltage is constructed by the Schottky barrier and a means to apply a stress to the barrier, the breakover voltage of the said semiconductor device can be controlled by the stress. If this device is assembled in a circuit system, the circuit system can be set to either the ''''off'''' or ''''on'''' state, corresponding to the applied stress.
Inventors
- 👤 Gota Kano
- 👤 Masami Yokozawa
- 👤 Tatsuo Kawasaki
- 👤 Shohei Fujiwara
- 👤 Hiromasa Hasegawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:16
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/50; G; G01; G01L; G01L1/00; G01L1/18; H10D99/00; H10P; H10P95/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
147 words
A method of manufacturing a pressure-sensitive PNPNsemiconductor device comprising the steps of a. forming a semiconductor layer having a given conductivity type on a first surface of a semiconductor substrate of the opposite conductivity type, b. forming a semiconductor region of said opposite conductivity type in said layer. c. depositing a metal film on the surface of said layer to form a Schottky barrier, d. depositing an ohmic electrode on said semiconductor region, e. depositing an alloy selected from the group consisting of gold-antimony and gold-gallium on a second surface of said semiconductor substrate opposite said first surface, and f. thermally fusing the surface of a metal base to said second surface of said semiconductor substrate, said alloy being interposed between said substrate and metal base, a region of said given conductivity type being formed in the process of fusing said metal base to said semiconductor substrate.
Claim 2
Independent Claim
147 words
A method of manufacturing a pressure-sensitive PNPNsemiconductor device comprising the steps of a. forming a semiconductor layer having a given conductivity type on a first surface of a semiconductor substrate of the opposite conductivity type, b. forming a semiconductor region of said opposite conductivity type in said layer. c. depositing a metal film on the surface of said layer to form a Schottky barrier, d. depositing an ohmic electrode on said semiconductor region, e. depositing an alloy selected from the group consisting of gold-antimony and gold-gallium on a second surface of said semiconductor substrate opposite said first surface, and f. thermally fusing the surface of a metal base to said second surface of said semiconductor substrate, said alloy being interposed between said substrate and metal base, a region of said given conductivity type being formed in the process of fusing said metal base to said semiconductor substrate.
Claim 3
Dependent Claim
40 words
A method of manufacturing a pressure-sensitive PNPN-semiconductor device as defined in claim 1 wherein said alloy is gold-antimony, said semiconductor substrate is P-type and an N-type region is formed during the fusing of said metal base to said semiconductor substrate.
Claim 4
Dependent Claim
24 words
A method of manufacturing a pressure sensitive semiconductor device according to claim 2, wherein the gold-antimony alloy includes 1-5 percent by weight of antimony.
Claim 5
Dependent Claim
41 words
A method of manufacturing a pressure-sensitive P-type semiconductor device as defined in claim 1 wherein said alloy is gold-gallium, said semiconductor substrate is N-type and a P-type region is formed during the fusing of said metal base to said semiconductor substrate.
Claim 6
Dependent Claim
24 words
A method of manufacturing a pressure sensitive semiconductor device accordinG to claim 4, wherein the gold-gallium alloy includes 4-10 percent by weight of gallium.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-17 | 1975-07-19 | 1976-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-17 | 1979-07-19 | 1980-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-17 | 1983-07-19 | 1984-01-18 | $7700.00 | Window Closed / Lapsed |