Four-layer semiconductor device strain switch

Claim 1

A STRAIN SWITCH COMPRISING A WAFER OF SEMICONDUCTOR MATERIAL HAVING A FOUR LAYERS OF ALTERNATE CONDUCTIVITY TYPES FORMING THREE JUNCTIONS; THE UPPER LAYER OF SAID FOUR LAYERS BEING DIVIDED INTO A FIRST AND SECOND PORTION; SAID FIRST AND SECOND PORTIONS HAVING A FIRST MAIN ELECTRODE AND A GATE ELECTRODE RESPECTIVELY CONNECTED THERETO; THE BOTTOM LAYER OF SAID FOUR LAYERS HAVING A SECOND MAIN ELECTRODE CONNECTED THERETO, AND BIAS CIRCUIT MEANS CONNECTED BETWEEN SAID FIRST MAIN ELECTRODE AND SAID GATE ELECTRODE FOR REVERSE BIASING THE JUNCTION FORMED BETWEEN SAID SECOND PORTION OF SAID UPPER LAYER AND THE LAYER OF SAID FOUR LAYERS ADJACENT SAID UPPER LAYER; AND MEANS FOR APPLYING A MECHANICAL STRAIN TO SAID LAST MENTIONED JUNCTION; SAID BIAS BEING NORMALLY INSUFFICIENT TO CAUSE CONDUCTION BETWEEN SAID FIRST AND SECOND MAIN ELECTRODES, SAID DEVICE BEING FIRED RESPONSIVE TO THE APPLICATION OF A PREDETERMINED STRAIN TO SAID DEVICE.