Analog-to-digital converter

Claim 2

In an analog-to-digital conversion system, the combination comprising, a transducer producing a variable output voltage, a free-running oscillator having a saturable core reactor with windings for driving tHe core to saturation alternately in opposite directions, a biasing winding on the core connected to the transducer for biasing the core to produce an output signal in the form of pulses of first and second polarity having a relative length which depends upon the condition of the transducer, an auxiliary oscillator having a frequency which is of higher order of magnitude than the frequency of the pulses from the source, a binary counter unit, means including a gate responsive to a pulse of first polarity for connecting the freerunning oscillator to the counter unit for storing a binary coded count representative of the length of the pulse of first polarity, an output line, reading means for connecting the binary counter unit to the output line for serial readout of the binary coded count stored in the counter unit, means responsive to a pulse of second polarity for disconnecting the auxiliary oscillator and for turning on the reading means, and means responsive to the completion of readout for turning off the reading means and for restoring the count in the binary counter unit to zero in readiness for reconnection to the auxiliary oscillator upon receipt of the next pulse of first priority.

Claim 3

The combination as claimed in claim 1 in which the frequency of the auxiliary oscillator is greater than the frequency of the free-running oscillator by two to approximately three magnitudes.

Claim 4

In an analog-to-digital conversion system, the combination comprising a source of periodic control pulses of alternating first and second polarity in which the length of a pulse of first polarity constitutes a measure of a variable, an auxiliary oscillator having a frequency which is higher by order of magnitude than the frequency of the pulses, a binary counter unit in the form of series-connected flip-flops, one for each binary order, means including a gate responsive to pulses of first polarity for connecting the auxiliary oscillator to the counter unit for storing a binary coded count representative of the width of a pulse of first polarity, an output line, reading means for coupling the flip-flops to the output line in sequence for producing successive pulses on said line representative of the binary coded count stored in said flip-flops, means responsive to a pulse of second polarity at said source for turning on the reading means, and means responsive to the reading of the last flip-flop in the series for turning off the reading means and for restoring the count in the flip-flops to zero in readiness for reconnection to the auxiliary oscillator upon receipt of the next control pulse of first polarity.

Claim 5

In an analog-to-digital conversion system, the combination comprising a source of periodic control pulses of alternating first and second polarity in which the length of a pulse of first polarity constitutes a measure of a variable, an auxiliary oscillator having a frequency which is higher by order of magnitude than the frequency of the pulses, a binary counter unit in the form of series-connected flip-flops, one for each binary order, means including a gate responsive to pulses of first polarity for connecting the auxiliary oscillator to the counter unit for storing a binary coded count representative of the width of a pulse of first polarity, an output line, reading means for coupling the flip-flops to the output line in sequence for producing successive pulses on said line representative of the binary coded count stored in said flip-flops, means responsive to a pulse of second polarity at said source for turning on the reading means, and means responsive to the reading of the last flip-flop in the series for turning off the reading means and for restoring the count in the flip-flops to zero in readiness for reconnection to the auxiliary oscillator upon receipt of the next control pulse of first polarity.

Claim 6

The combination as claimed in claim 3 in which the frequency of the auxiliary oscillator is on the order of 1000 times the frequency of the pulses from the source.

Claim 7

In an analog-to-digital conversion system, the combination comprising a source of periodic control pulses of alternating first and second polarity in which the length of a pulse of first polarity constitutes a measure of a variable, an auxiliary oscillator having a frequency which is higher by order of magnitude than the frequency of the pulses from the source, a binary counter unit in the form of series connected flip-flops, one for each binary order, means including a gate responsive to pulses of first polarity for connecting the source to the counter unit for storing a binary coded count representative of the length of a pulse of first polarity, an output line, a ring counter in the form of a ring of commutating flip-flops respectively coupled to the flip-flops in the counter unit, a commutating oscillator having a frequency which is lower tan that of the auxiliary oscillator for commutating the ring so that the flip-flops in the counter unit are successively connected to the output line to produce readout of a series of pulses on said line representative of the binary count stored in said counter unit, means responsive to the completion of readout for disconnecting the commutating oscillator from the ring coUnter and for restoring the count in the flip-flops of the binary counter unit to zero in readiness for reconnection of the storage unit to the auxiliary oscillator upon receipt of the next control pulse of first polarity.

Claim 8

In an analog-to-digital conversion system, the combination comprising a source of periodic control pulses of alternating first and second polarity in which the length of a pulse of first polarity constitutes a measure of a variable, an auxiliary oscillator having a frequency which is higher by order of magnitude than the frequency of the pulses from the source, a binary counter unit in the form of series connected flip-flops, one for each binary order, means including a gate responsive to pulses of first polarity for connecting the source to the counter unit for storing a binary coded count representative of the length of a pulse of first polarity, an output line, a ring counter in the form of a ring of commutating flip-flops respectively coupled to the flip-flops in the counter unit, a commutating oscillator having a frequency which is lower tan that of the auxiliary oscillator for commutating the ring so that the flip-flops in the counter unit are successively connected to the output line to produce readout of a series of pulses on said line representative of the binary count stored in said counter unit, means responsive to the completion of readout for disconnecting the commutating oscillator from the ring coUnter and for restoring the count in the flip-flops of the binary counter unit to zero in readiness for reconnection of the storage unit to the auxiliary oscillator upon receipt of the next control pulse of first polarity.

Claim 9

The combination as claimed in claim 5 in which the frequency of the auxiliary oscillator is on the order of a thousand times the frequency of the pulses from said source and in which the frequency of the commutating oscillator is a small fraction of the frequency of the auxiliary oscillator.

Claim 10

In an analog-to-digital conversion system, the combination comprising a transducer having a variable resistance, a free-running oscillator having a symmetrical circuit including a saturable core reactor with windings for alternate saturation of the core in opposite directions for producing half-wave output pulses of alternating first and second polarity, a biasing winding on the core coupled to the transducer and source of current for effective complementary shifting of the points of saturation thereby to change the relative length of the output pulses, an auxiliary oscillator having a frequency which is higher by order of magnitude compared to the frequency of the pulses from the free-running oscillator, a binary counter unit in the form of series connected stages, one for each order, means including a gate responsive to a pulse of first polarity for connecting the auxiliary oscillator to the counter unit for storing a binary coded count representative of the length of the pulse of first polarity, an output line, reading means including a commutating ring for connecting the stages of the counter unit to the output line in sequence for producing a succession of pulses on said line representative, order by order, of the binary coded count stored in said stages, means responsive to a pulse of second polarity from said source for turning on the reading means, and means responsive to completion of the cycle of the commutating ring for turning off the reading means and for restoring the count in the counter unit to zero in readiness for reconnection to the oscillator upon receipt of the next pulse of first polarity.

Claim 11

In an analog-to-digital conversion system, the combination comprising a transducer having a variable resistance, a free-running oscillator having a symmetrical circuit including a saturable core reactor with windings for alternate saturation of the core in opposite directions for producing half-wave output pulses of alternating first and second polarity, a biasing winding on the core coupled to the transducer and source of current for effective complementary shifting of the points of saturation thereby to change the relative length of the output pulses, an auxiliary oscillator having a frequency which is higher by order of magnitude compared to the frequency of the pulses from the free-running oscillator, a binary counter unit in the form of series connected stages, one for each order, means including a gate responsive to a pulse of first polarity for connecting the auxiliary oscillator to the counter unit for storing a binary coded count representative of the length of the pulse of first polarity, an output line, reading means including a commutating ring for connecting the stages of the counter unit to the output line in sequence for producing a succession of pulses on said line representative, order by order, of the binary coded count stored in said stages, means responsive to a pulse of second polarity from said source for turning on the reading means, and means responsive to completion of the cycle of the commutating ring for turning off the reading means and for restoring the count in the counter unit to zero in readiness for reconnection to the oscillator upon receipt of the next pulse of first polarity.

Claim 12

In an analog-to-digital conversion system, the combination comprising a transducer having a variable resistance, a free-running oscillator including first and second transistors and a saturable core reactor having windings respectively energized by the transistors, the transistors having cross-coupled input and output circuits for alternately driving the core to saturation in opposite directions to produce periodic half waves of output signal, a biasing winding on said core coupled to the transducer and source of current for effectively shifting the points of saturation to thereby change the relative length of the output pulses, an auxiliary source of high-frequency pulses having a constant repetition rate which is approximately two to three magnitudes greater than that of the pulses of the free-running oscillator, a binary counter, means including a gate interposed between the auxiliary source and the counter for connecting the auxiliary source to the counter for the duration of a pulse of first polarity from said oscillator and for disconnecting the auxiliary source from said counter for the duration of a pulse of second polarity so that a count is registered in said counter which is an accurate measure of the condition of said transducer.

Claim 13

In an analog-to-digital conversion system, the combination comprising a transducer having a variable resistance, a free-running oscillator including first and second transistors and a saturable core reactor having windings respectively energized by the transistors, the transistors having cross-coupled input and output circuits for alternately driving the core to saturation in opposite directions to produce periodic half waves of output signal, a biasing winding on said core coupled to the transducer and source of current for effectively shifting the points of saturation to thereby change the relative length of the output pulses, an auxiliary source of high-frequency pulses having a constant repetition rate which is approximately two to three magnitudes greater than that of the pulses of the free-running oscillator, a binary counter, means including a gate interposed between the auxiliary source and the counter for connecting the auxiliary source to the counter for the duration of a pulse of first polarity from said oscillator and for disconnecting the auxiliary source from said counter for the duration of a pulse of second polarity so that a count is registered in said counter which is an accurate measure of the condition of said transducer.