US3634702A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid-state delay line
Assignee: International Business Machines Corp
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Filing: 1969-12-12
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Granted: 1972-01-11
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Expires: 1989-12-12
Abstract
Abstract A solid-state delay line is disclosed which includes a field effect transistor with a gate electrode which is considerably extended in the direction of the semiconductor current channel. Two DC voltage sources are connected to the source and drain electrodes and to the ends of the gate electrode, respectively, and cause currents to be adjusted such that the voltage drops per unit length in the semiconductor channel and in the gate electrode are equal. A uniform thickness of the charge carrier variation zone, i.e., a depletion zone or an enhancement zone, is obtained in the semiconductor channel and the delay of signals propagating through the semiconductor channel is proportional to the length of the extended gate electrode.
Inventors
- 👤 Karsten E Drangeid
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:34
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/875; H03; H03H; H03H7/00; H03H7/30; H10D30/873
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
207 words
Delay line apparatus for delaying electrical signals comprising: a semiconductor channel having a given conductivity type; a source electrode means, a gate electrode means and a drain electrode means for establishing a field-effect transistor with said semiconductor channel; said gate electrode means including a gate electrode current conductive resistive path proximate to said semiconductor channel for establishing a variable charge carrier depletion zone of approximately uniform thickness in a length therein, a first DC voltage source means connected across said resistive path for establishing a DC current therein and a voltage drop thereacross along said channel, and means for establishing a uniform AC potential along said gate electrode resistive path; said source electrode means including a source electrode ohmic contact on said semiconductor channel; said drain electrode means including a drain electrode ohmic contact on semiconductor channel, and a second DC voltage source means connected between said source electrode ohmic contact and said drain electrode ohmic contact; a signal input terminal means connected to said source electrode ohmic contact and adapted to translate input signals to said semiconductor channel for delay therein; and a signal output terminal means connected to said drain electrode ohmic contact and adapted to translate said delayed input signals from said semiconductor channel.
Claim 2
Dependent Claim
207 words
Delay line apparatus for delaying electrical signals comprising: a semiconductor channel having a given conductivity type; a source electrode means, a gate electrode means and a drain electrode means for establishing a field-effect transistor with said semiconductor channel; said gate electrode means including a gate electrode current conductive resistive path proximate to said semiconductor channel for establishing a variable charge carrier depletion zone of approximately uniform thickness in a length therein, a first DC voltage source means connected across said resistive path for establishing a DC current therein and a voltage drop thereacross along said channel, and means for establishing a uniform AC potential along said gate electrode resistive path; said source electrode means including a source electrode ohmic contact on said semiconductor channel; said drain electrode means including a drain electrode ohmic contact on semiconductor channel, and a second DC voltage source means connected between said source electrode ohmic contact and said drain electrode ohmic contact; a signal input terminal means connected to said source electrode ohmic contact and adapted to translate input signals to said semiconductor channel for delay therein; and a signal output terminal means connected to said drain electrode ohmic contact and adapted to translate said delayed input signals from said semiconductor channel.
Claim 3
Dependent Claim
34 words
Delay line apparatus as set forth in claim 1 wherein said source electrode means includes a third DC voltage source means connected between said source electrode ohmic path and said gate electrode resistive path.
Claim 4
Dependent Claim
17 words
Delay line apparatus as set forth in claim 1 wherein said semiconductor channel is of N-type silicon.
Claim 5
Dependent Claim
26 words
Delay line apparatus as set forth in claim 1 wherein said resistive path of said gate electrode means establishes a Schottky-barrier junction with said semiconductor channel.
Claim 6
Dependent Claim
44 words
Delay line apparatus as set forth in claim 1 wherein said depletion zone is of approximately uniform thickness along said length of said semiconductor channel whereby a current channel of approximately uniform thickness is established in said semiconductor channel for delaying said input signals.
Claim 7
Dependent Claim
32 words
Delay line as set forth in claim 1 wherein said resistive path includes: a first plurality of partial gate electrodes; and a second plurality of resistances connecting sequentially said partial gate electrodes.
Claim 8
Dependent Claim
52 words
Delay line apparatus as set forth in claim 6 wherein said means for establishing said uniform AC potential along said resistive path includes a source of AC potential, and a first plurality of capacitances connected respectively to said first plurality of partial gate electrodes and to said source of said AC potential.
Claim 9
Dependent Claim
20 words
Delay line apparatus as set forth in claim 1 wherein said resistive path includes a continuous layer of resistive material.
Claim 10
Dependent Claim
19 words
Delay line apparatus as set forth in claim 8 wherein said continuous layer of resistive material consists of chromium.
Claim 11
Dependent Claim
58 words
Delay line apparatus as set forth in claim 8 wherein said means for establishing said uniform AC potential along said resistive path of said gate electrode means includes a source of AC potential an insulator layer On said layer of resistive material and a conductive layer on said insulator layer connected to said source of said AC potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-10 | 1975-07-12 | 1976-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-10 | 1979-07-12 | 1980-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-10 | 1983-07-12 | 1984-01-11 | $7700.00 | Window Closed / Lapsed |