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US3633005A Expired / Lapsed US ⏱️ 0.0 years remaining

A four quadrant multiplier using a single amplifier in a balanced modulator circuit

Assignee: International Business Machines Corp
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Filing: 1970-02-26
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Granted: 1972-01-04
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Expires: 1990-02-26
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Abstract

Abstract A multiplier circuit, having a relatively constant input impedance, capable of multiplying a positive or a negative input signal by a gain which is variable from a positive to a negative value by varying one control impedance. The input signal is applied to a reference input and to a signal input which includes a feedback path to provide both positive and negative products without the need for additional sign circuits or complimentary signals. The multiplier circuit can be adapted for use as a balanced modulator by providing an analog input signal and switching the control impedance between two different impedance values with a binary carrier signal.

Inventors

  • 👤 Howard N Leighton

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 05:51
CPC Classifications
G; G06; G06J; G06J1/00; H; H03; H03C; H03C1/00; H03C1/52; H03C1/54; H03C1/542; H03C1/545; H03F; H03F3/00; H03F3/72; H03K; H03K7/00; H03K7/02

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 107 words
A multiplier comprising: operational amplifier means having a first and a second input terminal and an output terminal; signal input means connected to a first terminal of a reference input impedance and to a first terminal of an input impedance; reference impedance means connected between said first input terminal and a ground reference potential; said reference input impedance and said input impedance each having a second terminal connected to said first and second input terminals respectively; feedback impedance means connected between said output terminal and said second input terminal; variable-impedance means connected between said second input terminal and ground for controlling the gain of said operational amplifier.
Claim 2
Dependent Claim 107 words
A multiplier comprising: operational amplifier means having a first and a second input terminal and an output terminal; signal input means connected to a first terminal of a reference input impedance and to a first terminal of an input impedance; reference impedance means connected between said first input terminal and a ground reference potential; said reference input impedance and said input impedance each having a second terminal connected to said first and second input terminals respectively; feedback impedance means connected between said output terminal and said second input terminal; variable-impedance means connected between said second input terminal and ground for controlling the gain of said operational amplifier.
Claim 3
Dependent Claim 34 words
The multiplier as defined in claim 1 wherein said bias impedance means and said first impedance means are of equal value; and said first impedance means is one-half the value of said feedback impedance.
Claim 4
Dependent Claim 26 words
The multiplier as defined in claim 2 wherein said variable-impedance control means is variable between the values of one-half the feedback impedance to an infinite impedance.
Claim 5
Dependent Claim 25 words
The multiplier of claim 3 further comprising control means for switching said variable control impedance in response to the condition of a binary input signal.
Claim 6
Dependent Claim 91 words
The multiplier of claim 1 wherein said variable control impedance comprises: a plurality of digital input terminals for accepting a binary word, a plurality of switching means each connected to one of said digital input terminals; a plurality of gain control resistors each connected to a separate one of said switching means; said plurality of gain control resistors connected to said second input terminal; whereby said switch means selectively engages combinations of said gain control resistors to said second input terminal so as to control the gain of said operational amplifier.

References Cited (Backward Citations)

US3013724A Cited
US3324416A Cited
US3389327A Cited
US3384840A Cited
US3469080A Cited
US3484589A Cited
US3525860A Cited
US3484595A Cited
US3473043A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-01-03 1975-07-05 1976-01-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-01-03 1979-07-05 1980-01-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-01-03 1983-07-05 1984-01-04 $7700.00 Window Closed / Lapsed

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