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Patent US3632876A successfully refreshed from Google Patents.
US3632876A
Expired / Lapsed
US
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Binary to pulse waveform converter
Assignee: Motorola Solutions Inc
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Filing: 1969-10-16
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Granted: 1972-01-04
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Expires: 1989-10-16
Abstract
Abstract A sequence of binary data bits are transformed into a waveform consisting of a series of half-cycles of square waves of two different frequencies, the half-cycles being of alternating phase and each frequency corresponding to one of the two binary conditions. This sequence of half-cycle square waves then may be transmitted as a stream of exact half-cycles of audio tones.
Inventors
- 👤 Stephen M Bench
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:37
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/24
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
268 words
A system for converting a train of binary data bits into a sequence of pulses of at least two different widths, pulses of one width corresponding to data bits of one condition and pulses of another width corresponding to data bits of anoTher condition, including in combination: a source of data bits having first and second outputs with an enabling signal appearing on the first output for data bits of said one condition and an enabling signal appearing on the second output for data bits of said other condition; first and second gating means enabled by enabling signals on the first and second outputs, respectively, of the source of data bits; timing means having first and second outputs and operable for producing pulses thereon at first and second time intervals, respectively, following initiation of operation of the timing means, with the first output of the timing means being coupled with the first gating means and with the second output of the timing means being coupled with the second gating means, the first and second gating means each providing an output pulse whenever the corresponding gating means is enabled at the time of occurrence of a pulse on the respective output of the timing means; means coupled with the first and second gating means and responsive to an output pulse from either of said gating means for causing the next data bit to be supplied to the outputs of the source of data bits; and means for providing an output signal, the phase of which reverses each time an output pulse is obtained form either of the gating means.
Claim 2
Independent Claim
268 words
A system for converting a train of binary data bits into a sequence of pulses of at least two different widths, pulses of one width corresponding to data bits of one condition and pulses of another width corresponding to data bits of anoTher condition, including in combination: a source of data bits having first and second outputs with an enabling signal appearing on the first output for data bits of said one condition and an enabling signal appearing on the second output for data bits of said other condition; first and second gating means enabled by enabling signals on the first and second outputs, respectively, of the source of data bits; timing means having first and second outputs and operable for producing pulses thereon at first and second time intervals, respectively, following initiation of operation of the timing means, with the first output of the timing means being coupled with the first gating means and with the second output of the timing means being coupled with the second gating means, the first and second gating means each providing an output pulse whenever the corresponding gating means is enabled at the time of occurrence of a pulse on the respective output of the timing means; means coupled with the first and second gating means and responsive to an output pulse from either of said gating means for causing the next data bit to be supplied to the outputs of the source of data bits; and means for providing an output signal, the phase of which reverses each time an output pulse is obtained form either of the gating means.
Claim 3
Dependent Claim
27 words
The combination according to claim 1 further including means for resetting the timing means each time an output pulse is obtained from either of the gating means.
Claim 4
Independent Claim
269 words
A system for converting trains of binary data bits into a sequence of pulses of two different widths, pulses of one width corresponding to data bits of one binary condition and pulses of another width corresponding to data bits of another binary condition, including in combination: a source of binary data bits having first and second outputs, with an enabling signal appearing on the first output for data bits of said one binary condition and an enabling signal appearing on the second output for data bits of said other binary condition; first and second gating means enabled by enabling signals on the first and second outputs, respectively, of the source of binary data bits; counter means having at least two outputs, corresponding to first and second counts, the output corresponding to the first count being coupled with the first gating means and the output corresponding to the second count being coupled with the second gating means, the first and second gating means each providing an output pulse whenever the corresponding gating means is enabled at the time of occurrence of the respective count reached by the counter means; a source of clock pulses for driving the counter means; means coupled with the first and second gating means and responsive to an output pulse from either of said gating means for resetting the counter means and for causing the next data bit to be supplied to the outputs of the source of binary data bits; and means for providing an output signal, the phase of which reverses each time an output pulse is obtained from either of said gating means.
Claim 5
Independent Claim
269 words
A system for converting trains of binary data bits into a sequence of pulses of two different widths, pulses of one width corresponding to data bits of one binary condition and pulses of another width corresponding to data bits of another binary condition, including in combination: a source of binary data bits having first and second outputs, with an enabling signal appearing on the first output for data bits of said one binary condition and an enabling signal appearing on the second output for data bits of said other binary condition; first and second gating means enabled by enabling signals on the first and second outputs, respectively, of the source of binary data bits; counter means having at least two outputs, corresponding to first and second counts, the output corresponding to the first count being coupled with the first gating means and the output corresponding to the second count being coupled with the second gating means, the first and second gating means each providing an output pulse whenever the corresponding gating means is enabled at the time of occurrence of the respective count reached by the counter means; a source of clock pulses for driving the counter means; means coupled with the first and second gating means and responsive to an output pulse from either of said gating means for resetting the counter means and for causing the next data bit to be supplied to the outputs of the source of binary data bits; and means for providing an output signal, the phase of which reverses each time an output pulse is obtained from either of said gating means.
Claim 6
Dependent Claim
60 words
The combination according to claim 3 wherein the means for resetting the counter means and the means for providing the output signal comprise first and second bistable devices, respectively, with the second bistable device being a complementary bistable multivibrator, the state of which changes each time an output pulse is obtained from either of the first and second gating means.
Claim 7
Dependent Claim
39 words
The combination according to claim 3 further including means for establishing a predetermined phase of the output signal of the output of the means for providing said output signal for the first data bit being converted by the system.
Claim 8
Dependent Claim
54 words
The combination according to claim 3 further including means responsive to an even count of the data bits being converted for adding and converting to the train of data bits a data bit of a predetermined one of the binary conditions to cause the system to always convert an odd number of data bits.
Claim 9
Dependent Claim
37 words
The combination according to claim 3 wherein the source of binary data bits is a shift register, the output stage of which has said first and second outputs and wherein the counter means is a binary counter.
Claim 10
Dependent Claim
61 words
The combination according to claim 7 wherein the second count is higher than the first count and the first and second counts are sufficiently separated so that the time required to step the counter from its reset condition to the first count is substantially less than the time required to step the counter from its reset condition to the second count.
Claim 11
Independent Claim
337 words
A system for converting digital waveforms comprising trains of binary input signals into a sequence of pulses of two different widths, the pulses of one width corresponding to input signals of one binary condition and pulses of the other width corresponding to input signals of another binary condition, the system including in combination: a shift register supplied with binary input signals to be converted and having an output stage with first and second outputs, an enabling signal appearing on the first output with a binary signal of said one condition appearing in the output stage and an enabling signal appearing on the second output with a binary signal of said other condition appearing in the output stage; first and second gating means enabled by enabling signals on the first and second outputs, respectively, of the output stage of the shift register; a binary counter means having an output corresponding to a first binary count coupled with an input to the first gating means and having an output corresponding to a second binary count coupled with an input to the second gating means, each gating means providing an output pulse whenever the gating means is enabled at the time the corresponding respective count is reached by the binary counter; a source of clock pulses for stepping the binary counter, said clock pulses being counted in the binary counter for producing the first and second counts therein; a first bistable multivibrator responsive to the output pulses of the first and second gating means for resetting the counter whenever an output pulse is obtained from either of the gating means and for providing a shift pulse to the shift register to present the next binary signal to the output stage thereof; and a complementary bistable multivibrator responsive to the resetting of the counter for providing a train of output pulses, the phase of which reverses each time the counter is reset after reaching the first or second counts to trigger the complementary bistable multivibrator into a different state of operation.
Claim 12
Independent Claim
337 words
A system for converting digital waveforms comprising trains of binary input signals into a sequence of pulses of two different widths, the pulses of one width corresponding to input signals of one binary condition and pulses of the other width corresponding to input signals of another binary condition, the system including in combination: a shift register supplied with binary input signals to be converted and having an output stage with first and second outputs, an enabling signal appearing on the first output with a binary signal of said one condition appearing in the output stage and an enabling signal appearing on the second output with a binary signal of said other condition appearing in the output stage; first and second gating means enabled by enabling signals on the first and second outputs, respectively, of the output stage of the shift register; a binary counter means having an output corresponding to a first binary count coupled with an input to the first gating means and having an output corresponding to a second binary count coupled with an input to the second gating means, each gating means providing an output pulse whenever the gating means is enabled at the time the corresponding respective count is reached by the binary counter; a source of clock pulses for stepping the binary counter, said clock pulses being counted in the binary counter for producing the first and second counts therein; a first bistable multivibrator responsive to the output pulses of the first and second gating means for resetting the counter whenever an output pulse is obtained from either of the gating means and for providing a shift pulse to the shift register to present the next binary signal to the output stage thereof; and a complementary bistable multivibrator responsive to the resetting of the counter for providing a train of output pulses, the phase of which reverses each time the counter is reset after reaching the first or second counts to trigger the complementary bistable multivibrator into a different state of operation.
Claim 13
Dependent Claim
47 words
The combination according to claim 9 further including means for initially setting the complementary bistable multivibrator to a predetermined output condition in response to the initial appearance of an enabling signal on either of said first and second outputs of the last stage of the shift register.
Claim 14
Dependent Claim
74 words
The combination according to claim 10 further including means responsive to the enabling signals on the first and second outputs of the last stage of the shift register and further responsive to a predetermined state of operation of the complementary bistable multivibrator for sensing a predetermined relationship between enabling signals and the state of operation of the complementary bistable multivibrator for changing the state of the complementary bistable multivibrator whenever such predetermined condition exists.
Claim 15
Dependent Claim
53 words
The combination according to claim 11 wherein the means for changing the state of the complementary multivibrator operates when no enabling signals are obtained from the output stage of the shift register and the state of operation of the complementary bistable multivibrator indicates an even number of binary input signals has been converted.
References Cited (Backward Citations)
US3251051A
Cited
US3461237A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-03 | 1975-07-05 | 1976-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-03 | 1979-07-05 | 1980-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-03 | 1983-07-05 | 1984-01-04 | $7700.00 | Window Closed / Lapsed |