Input and output circuitry

Claim 2

A periodically operating digital circuit comprising: at least one logic network which provides an output signal in response to an input signal applied thereto, said output signal being logically dependent upon said input signal; converter means having a plurality of parallel inputs and a plurality of parallel outputs responsive to an input signal applied thereto for causing, during a first portion of each cycle of operation, signals to simultaneously appear at selected ones of said parallel outputs, and said converter means, in response to signals applied to selected ones of said parallel inputs thereof during a second portion of each cycle of operation, causing an output signal to be provided thereby; means for applying to said logic network, as said input signal thereof, one of the signals caused to appear at said parallel outputs of said converter means; and means for applying during said second portion of each cycle of operation said output signal provided by said logic network to one of said parallel inputs of said converter means.

Claim 3

The invention according to claim 1 wherein said converter means includes means for providing said output signal during the first portion of the cycle of operation immediately following the cycle of operation in which said signals, to which said output signal is in response, are applied to said selected parallel inputs.

Claim 4

The invention according to claim 1 wherein said converter means includes a shift register having a serial input, a serial output, and a plurality of parallel input-outputs, said converter means input signal being applied to said serial input of said shift register and including a plurality of informational bit signals which occur one after another in serial order during said first portion of each cycle of operation, said shift register causing a signal corresponding to a different one of each of said bits applied to said serial input thereof to appear simultaneously and in parallel at a predetermined one of each of said input-outputs at the end of said first portion of each cycle of operation, one of said signals caused to appear at said input-outputs being the signal applied to said logic network, said one signal caused to appear at said input-outputs being replaced by the signal provided by said logic network during said second portion of said cycle of operation, said shift register causing said signals which appear at each of said input-outputs at the end of said second portion of each cycle of operation to be thereafter applied, one after another in serial order, at said serial output thereof as said converter means output signal.

Claim 5

The invention according to claim 3 wherein said converter means includes means for providing said output signal during the first portion of the cycle of operation immediately following the cycle of operation during which said one signal is caused to appear at said input-outputs of said shift register.

Claim 6

The invention according to claim 1 wherein said converter means includes an input shift register and an output shift register, said input shift register having a serial input and a plurality of parallel outputs and said output shift register having a plurality of parallel inputs and a serial output, said converter means input signal being applied to said serial input of said input shift register and including a plurality of informational bit signals which occur one after another in serial order during the first portion of each cycle of operation, said input shift register causing a signal corresponding to a different one of each said bits applied to said serial input thereof to appear simultaneously and in parallel order at a predetermined one of each of said parallel outputs thereof at the end of said first portion of each cycle of operation; one of said signals appearing at said parallel outputs of said input shift register being the signal applied to said logic network, said output signal provided by said logic network being applied to one of said parallel inputs of said output shift register, said output shift register causing all of the signals which are applied to said parallel inputs thereof to be thereafter applied, one after another in serial order, at said serial output thereof as said converter means output signal.

Claim 7

The invention according to claim 5 wherein said converter means includes means for providing said output signal during the first portion of the cycle of operation immediately following the cycle of operation during which said one signal is caused to appear at one of said parallel outputs of said input shift register.

Claim 8

In combination: a shift register having at least two stages, there being a given bit of information in a given one of said stages; logic means remote from said shift register responsive to the application thereto of said given bit of information for providing a new logically different bit of information which is a logical function of said given bit of information; and means coupling said logic means to said given stage for caUsing said given bit of information to be replaced by said new bit of information; said shift register thereafter causing said new bit of information to be shifted to a new stage.

Claim 9

In combination: a shift register having at least two stages, there being a given bit of information in a given one of said stages; logic means remote from said shift register responsive to the application thereto of said given bit of information for providing a new logically different bit of information which is a logical function of said given bit of information; and means coupling said logic means to said given stage for caUsing said given bit of information to be replaced by said new bit of information; said shift register thereafter causing said new bit of information to be shifted to a new stage.

Claim 10

The invention according to claim 7 in which said shift register includes in each stage thereof semiconductor devices which can store a signal for a time longer than the time necessary to shift a bit from one stage to the next succeeding stage of said shift register, and which can allow a signal which is stored thereby to be replaced by a new signal which is to be stored thereby in a time less than the time necessary to shift a bit from one stage to the next succeeding stage of said shift register, said stored signals representing bits of information.

Claim 11

The invention according to claim 7 in which said shift register includes field effect transistors arranged in a multiphase switching circuit configuration.

Claim 12

The invention according to claim 7: wherein said new bit providing means includes means for storing a signal corresponding to said given bit for a time at least as long as the time required to provide said new bit; wherein said shift register includes means to store a signal corresponding to a bit of information; and wherein means are further included for allowing the signal stored in said shift register which corresponds to said given bit to assume a given value value prior to the time said new bit is provided.

Claim 13

The invention according to claim 10 wherein said means for allowing further includes means for causing said signal stored in said shift register to assume a value corresponding to said new bit after it has assumed said given value.

Claim 14

The invention according to claim 7 in which said given stage of said shift register is located on one integrated circuit chip and said new stage is located on another integrated circuit chip.

Claim 15

In combination: a shift register having at least two stages, there being a given bit of information in a given one of said stages; means for shifting said given bit of information from one of said stages to another one of said stages during a first portion of each cycle of operation; and logic means remote from said shift register for causing said given bit of information to be replaced by a new logically different bit of information during a different unique second portion of said cycle, said new bit of information being logically dependent upon said given bit of information.

Claim 16

In combination: a shift register having at least two stages, there being a given bit of information in a given one of said stages; means for shifting said given bit of information from one of said stages to another one of said stages during a first portion of each cycle of operation; and logic means remote from said shift register for causing said given bit of information to be replaced by a new logically different bit of information during a different unique second portion of said cycle, said new bit of information being logically dependent upon said given bit of information.

Claim 17

The invention according to claim 13 wherein said means for shifting further includes means for causing said new bit of information to be shifted to a third stage of said shift register during a first portion of the next cycle of operation and thereafter replaced with a third bit of information during a second portion of said next cycle, said third bit of information being logically dependent upon said new bit of information.

Claim 18

The invention according to claim 14 in which said shift register includes field effect transistors arranged in a multiphase switching circuit configuration.

Claim 19

The invention according to claim 14: wherein said logic means includes means for storing a signal corresponding to said given bit for a time at least as long as the time required to provide a signal which corresponds to said new bit; wherein said shift register includes means to store a signal corresponding to a bit of information; and wherein means are further included for allowing the signal stored in said shift register which corresponds to said given bit to assume a given value prior to the time said given bit is replaced.

Claim 20

The invention according to claim 16 wherein said signal stored in said shift register is caused to assume a value corresponding to said new bit after it has assumed said given value.

Claim 21

The invention according to claim 13 in which said one stage of said shift register is located on one integrated circuit chip and said another stage of said shift register is located on a second integrateD circuit chip.

Claim 22

The invention according to claim 13 wherein said logic means includes a logic circuit which in response to a signal applied thereto provides a signal which is logically dependent upon said signal so applied, first coupling means for coupling the signal appearing at said another stage of said shift register to said logic circuit only during said first portion of said cycle, and second coupling means for coupling said signal provided by said logic circuit to said another stage of said shift register only during said second portion of said cycle.

Claim 23

On an integrated circuit chip which includes a plurality of periodically operating logic circuits each of which during each cycle of operation performs a logical operation and provides an output signal which is in accordance with the logical operation so performed; and at least one output means which includes an output pad; circuitry included on said chip for translating said output signals to said output means comprising: a converter having an output and a plurality of inputs for converting a plurality of signals which are applied in parallel to said inputs thereof to a single signal which manifests each of said parallel applied signals in a predetermined serial order; first coupling means for causing each of said logic circuit output signals to be applied to a respective one of said converter inputs; and second coupling means for coupling said converter signal output to said output means; said logic circuits operating during a first portion of said cycle and said converter operating during a second portion of said cycle.

Claim 24

On an integrated circuit chip which includes a plurality of periodically operating logic circuits each of which during each cycle of operation performs a logical operation and provides an output signal which is in accordance with the logical operation so performed; and at least one output means which includes an output pad; circuitry included on said chip for translating said output signals to said output means comprising: a converter having an output and a plurality of inputs for converting a plurality of signals which are applied in parallel to said inputs thereof to a single signal which manifests each of said parallel applied signals in a predetermined serial order; first coupling means for causing each of said logic circuit output signals to be applied to a respective one of said converter inputs; and second coupling means for coupling said converter signal output to said output means; said logic circuits operating during a first portion of said cycle and said converter operating during a second portion of said cycle.

Claim 25

The invention according to claim 20 wherein said first coupling means causes said logic circuit output signals to be applied to said converter during said first portion of said cycle.

Claim 26

The invention according to claim 20 further including clocking means for providing two sets of periodic clock signals, each signal of said first set of clock signals having a single uniquely defined pulse which can only occur during said first portion of said cycle and each signal of said second set of clock signals having a plurality of uniquely defined periodic pulses which can only occur during said second portion of said cycle, said first set of clock signals being applied to said logic circuits and said second set of clock signals being applied to said converter.

Claim 27

The invention according to claim 22: wherein said two sets of clock signals are multiphase switching circuit signals; wherein said logic circuits include multiphase switching circuits arranged to perform logical operations; and wherein said converter includes multiphase switching circuits arranged as a serial-in, parallel-out shift register.

Claim 28

A circuit for performing a plurality of logical operations during a first given time in a cycle and for transferring the results of each of said logical operations so performed to an output during a second given time, in said cycle, said circuit comprising: means for providing two sets of clock signals during said cycle, said first set including four signals, each of which has one uniquely defined pulse during said first given time in each cycle and said second set including four signals, each of which has one chain of uniquely defined pulses during said second given time in each cycle, the pulses of said second set of signals occurring after the pulses of said first set of signals have occurred; a plurality of logic networks each of which in response to an input signal and in response to two of said four signals of said first set of clock signals provides an output signal which is a logical function of said input signal, a parallel-in, serial-out shift register having a plurality of inputs and a single output, said logic network output signals being applied in parallel to said inputs of said shift register during said first given time and said shift register providing a signal at its output during said second giveN time, said shift register output signal being a serial version of said logic network output signals; and means for coupling the output of said shift register to the output of said circuit.

Claim 29

A circuit for performing a plurality of logical operations during a first given time in a cycle and for transferring the results of each of said logical operations so performed to an output during a second given time, in said cycle, said circuit comprising: means for providing two sets of clock signals during said cycle, said first set including four signals, each of which has one uniquely defined pulse during said first given time in each cycle and said second set including four signals, each of which has one chain of uniquely defined pulses during said second given time in each cycle, the pulses of said second set of signals occurring after the pulses of said first set of signals have occurred; a plurality of logic networks each of which in response to an input signal and in response to two of said four signals of said first set of clock signals provides an output signal which is a logical function of said input signal, a parallel-in, serial-out shift register having a plurality of inputs and a single output, said logic network output signals being applied in parallel to said inputs of said shift register during said first given time and said shift register providing a signal at its output during said second giveN time, said shift register output signal being a serial version of said logic network output signals; and means for coupling the output of said shift register to the output of said circuit.

Claim 30

On an integrated circuit chip which includes input means to which an input signal is applied and a plurality of logic circuits each of which during a first given time and in response to a signal applied to an input thereof provides a signal at an output thereof which is a logical function of said signal applied thereto, said input signal including a plurality of individual signals arranged in a serial order, circuitry for causing each of said plurality of individual signals to be applied to a respective one of said plurality of logic circuits, said circuitry comprising: a converter having an input and a plurality of outputs, said input being coupled to said input means such that said input signal is applied to said converter input, and responsive to a timing signal associated therewith at the end of a second given time, which occurs prior to said first given time period, for causing a different one of said individual signals to be provided at a respective one of said converter outputs; and means for coupling each of said converter outputs to a respective one of said logic circuits.

Claim 31

On an integrated circuit chip which includes input means to which an input signal is applied and a plurality of logic circuits each of which during a first given time and in response to a signal applied to an input thereof provides a signal at an output thereof which is a logical function of said signal applied thereto, said input signal including a plurality of individual signals arranged in a serial order, circuitry for causing each of said plurality of individual signals to be applied to a respective one of said plurality of logic circuits, said circuitry comprising: a converter having an input and a plurality of outputs, said input being coupled to said input means such that said input signal is applied to said converter input, and responsive to a timing signal associated therewith at the end of a second given time, which occurs prior to said first given time period, for causing a different one of said individual signals to be provided at a respective one of said converter outputs; and means for coupling each of said converter outputs to a respective one of said logic circuits.

Claim 32

The invention according to claim 25 further including clocking means which provide two sets of periodic clock signals, the period of each signal in each set of said clock signals being identical and equal to said first given time plus said second given time, each signal of said first set of clock signals having a fixed number of pulses which can occur only during said first time, said fixed number depending upon the number of individual signals included in said input signal, and each signal of said second set of clock pulses having at least one pulse which can occur only during said second time, said first set of clock signals being applied to said converting means as said control signal associated therewith and said second set of control signals being applied to said logic circuits to cause said logic circuits to provide said output signals.

Claim 33

The invention according to claim 26 wherein said two sets of clock signals are multiphase switching circuits signals, wherein said logic circuits are multiphase logic circuits; and wherein said converter is a multiphase serial-in, parallel-out shift register.

Claim 34

Circuitry on an integrated circuit chip for performing M logical operations during each cycle of operation in response to the application to said circuitry through a single pad on said integrated circuit chip of an input signal which includes a plurality of serially arranged periodic bit chains, each of said bit chains including N serially arranged bits of information, all of which occur during a first portion of each cycle of operation, at least one of said logical operations during each cycle being in response to at least one of said bits of information in the chain of N bits of information occurring in that cycle, said logical operations occurring during a second portion of each cycle, said circuitry comprising: means for providing first and second sets of periodic four-phase switching circuit clock signals, each signal of said first set of clock signals having during each cycle at least N pulses all of which occur only during said first portion of said cycle and each signal of said second set of clock signals having during each cycle a single pulse which occurs only during said second portion of said cycle; a serial-in, parallel-out, four-phase controlled shift register having at least N stages, said input signal being applied to a serial input of said shift register, said first set of clock pulses being applied to clocking inputs of said shift register, and each of said N bits of information appearing at one given one of at least N parallel outputs of said shift register after the last pulse of said first set of clock signals has oCcurred; and M logic circuits to each of which information signals are applied, at least one of said information signals which is applied to at least one of said logic circuits being the signal appearing at one of said N parallel outputs of said shift register and to each of which at least two of the signals of said second set of clocking signals are applied, each of said logic circuits providing an output signal during said second portion of said cycle, said signal being a logical function of the information signals applied thereto.

Claim 35

Circuitry on an integrated circuit chip for performing M logical operations during each cycle of operation in response to the application to said circuitry through a single pad on said integrated circuit chip of an input signal which includes a plurality of serially arranged periodic bit chains, each of said bit chains including N serially arranged bits of information, all of which occur during a first portion of each cycle of operation, at least one of said logical operations during each cycle being in response to at least one of said bits of information in the chain of N bits of information occurring in that cycle, said logical operations occurring during a second portion of each cycle, said circuitry comprising: means for providing first and second sets of periodic four-phase switching circuit clock signals, each signal of said first set of clock signals having during each cycle at least N pulses all of which occur only during said first portion of said cycle and each signal of said second set of clock signals having during each cycle a single pulse which occurs only during said second portion of said cycle; a serial-in, parallel-out, four-phase controlled shift register having at least N stages, said input signal being applied to a serial input of said shift register, said first set of clock pulses being applied to clocking inputs of said shift register, and each of said N bits of information appearing at one given one of at least N parallel outputs of said shift register after the last pulse of said first set of clock signals has oCcurred; and M logic circuits to each of which information signals are applied, at least one of said information signals which is applied to at least one of said logic circuits being the signal appearing at one of said N parallel outputs of said shift register and to each of which at least two of the signals of said second set of clocking signals are applied, each of said logic circuits providing an output signal during said second portion of said cycle, said signal being a logical function of the information signals applied thereto.

Claim 36

Circuitry on an integrated circuit chip for performing M logical operations during each cycle of operation in response to the application to said circuitry through an input pad on said integrated circuit chip of an input signal which includes a plurality of serially arranged periodic bit chains, each of said bit chains including N serially arranged bits of information all of which occur during a first portion of each cycle of operation, at least one of said logical operations during each cycle being in response to at least one of said bits of information in the chain of N bits of information occurring in that cycle, said logical operations occuring during a second portion of each cycle, said circuitry further providing an output signal during the first portion of said cycle which includes a chain of N bits of information, at least one of said N bits of information of said output signal corresponding to the signal resulting from a logical operation performed during a prior cycle of operation, said circuitry comprising: means for providing first and second sets of phased switching clock signals, each signal of said first set of clock signals having during each cycle at least N pulses all of which occur only during said first portion of said cycle and each signal of said second set of clock signals having during each cycle a signal pulse which occurs only during said second portion of said cycle, means for applying said first set of clock signals and said input signal to a shift register, said shift register causing each one of said N bits of information which occur during each cycle to appear at a respective one of N outputs of said shift register after the last pulse of said first set of clock signals has occurred, during that cycle; M logic circuit responsive to the application of said signals appearing at each of said N outputs of said shift register for providing at an output thereof signal which is a logical function of said signals so applied, said logic circuits providing said signals during said second portion of each cycle; means for coupling the output of at least one of said logic circuits to one of N parallel inputs of a shift register, whereby said one logic circuit output signal is stored in said shift register having said N parallel inputs; said shift register having said N parallel inputs providing a serial output there of a chain of bits, during the first portion of said next cycle of operation, one of said bits representing said signal from said one logic circuit.

Claim 37

Circuitry on an integrated circuit chip for performing M logical operations during each cycle of operation in response to the application to said circuitry through an input pad on said integrated circuit chip of an input signal which includes a plurality of serially arranged periodic bit chains, each of said bit chains including N serially arranged bits of information all of which occur during a first portion of each cycle of operation, at least one of said logical operations during each cycle being in response to at least one of said bits of information in the chain of N bits of information occurring in that cycle, said logical operations occuring during a second portion of each cycle, said circuitry further providing an output signal during the first portion of said cycle which includes a chain of N bits of information, at least one of said N bits of information of said output signal corresponding to the signal resulting from a logical operation performed during a prior cycle of operation, said circuitry comprising: means for providing first and second sets of phased switching clock signals, each signal of said first set of clock signals having during each cycle at least N pulses all of which occur only during said first portion of said cycle and each signal of said second set of clock signals having during each cycle a signal pulse which occurs only during said second portion of said cycle, means for applying said first set of clock signals and said input signal to a shift register, said shift register causing each one of said N bits of information which occur during each cycle to appear at a respective one of N outputs of said shift register after the last pulse of said first set of clock signals has occurred, during that cycle; M logic circuit responsive to the application of said signals appearing at each of said N outputs of said shift register for providing at an output thereof signal which is a logical function of said signals so applied, said logic circuits providing said signals during said second portion of each cycle; means for coupling the output of at least one of said logic circuits to one of N parallel inputs of a shift register, whereby said one logic circuit output signal is stored in said shift register having said N parallel inputs; said shift register having said N parallel inputs providing a serial output there of a chain of bits, during the first portion of said next cycle of operation, one of said bits representing said signal from said one logic circuit.