Patent US3631350A successfully refreshed from Google Patents.
US3631350A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronous counting apparatus
Assignee: Collins Radio Co
•
Filing: 1970-09-15
•
Granted: 1971-12-28
•
Expires: 1990-09-15
Abstract
Abstract Apparatus for and the method of obtaining high-speed synchronous counting at speeds and an accuracy which would normally encounter problems due to delays in steering circuits used with the counting flip-flops. This is accomplished by the use of a synchronous AND gate operating in conjunction with a first section of flip-flops for controlling the remaining section of flip-flops.
Inventors
- 👤 John Vernon Drake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:03
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
153 words
Synchronous counting apparatus comprising, in combination: a first section of multiple AND input J-K flip-flop stages, each stage connected to effectively receive the outputs of all previous stages in said first section; a second section of multiple AND input J-K flip-flop stages, each stage connected to effectively receive the outputs of all previous stages in said second section; means for supplying periodically occurring signals to be counted to each stage; and synchronous AND gate means, comprising multiple AND input J-K flip-flop means, connecting said first section to said second section for supplying to the stages of said second section a signal representative of the logical ANDing of the outputs of all stages of said first section, the J-input of said flip-flop of said AND gate means connected for receiving inputs from said first section and the Q-output thereof connected for supplying signals to said second section and to the K-input of said flipflop.
Claim 2
Dependent Claim
153 words
Synchronous counting apparatus comprising, in combination: a first section of multiple AND input J-K flip-flop stages, each stage connected to effectively receive the outputs of all previous stages in said first section; a second section of multiple AND input J-K flip-flop stages, each stage connected to effectively receive the outputs of all previous stages in said second section; means for supplying periodically occurring signals to be counted to each stage; and synchronous AND gate means, comprising multiple AND input J-K flip-flop means, connecting said first section to said second section for supplying to the stages of said second section a signal representative of the logical ANDing of the outputs of all stages of said first section, the J-input of said flip-flop of said AND gate means connected for receiving inputs from said first section and the Q-output thereof connected for supplying signals to said second section and to the K-input of said flipflop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-27 | 1975-06-28 | 1975-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-27 | 1979-06-28 | 1979-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-27 | 1983-06-28 | 1983-12-28 | $7700.00 | Window Closed / Lapsed |