Patent US3629709A successfully refreshed from Google Patents.
US3629709A
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US
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Electronic frequency converter
Assignee: Ebauches SA
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Filing: 1969-12-17
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Granted: 1971-12-21
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Expires: 1989-12-17
Abstract
Abstract An electronic frequency converter for digitally converting the frequency of a first pulse series at a frequency corresponding to mean time or atomic time into a pulse series at a frequency corresponding to sidereal time by pulse addition and pulse subtraction.
Inventors
- 👤 Jean Engdahl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:56
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; G04G3/022; H; H03; H03B; H03B21/00; H03B21/01; H03B21/02; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/662
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
139 words
An electronic frequency converter for transforming a frequency corresponding to mean time time into a frequency corresponding to sidereal time, comprising an input circuit for producing a pulse series at an input frequency corresponding to mean time, a first-converting circuit including a first-frequency divider and a pulse-adding stage, said input circuit being connected to said pulse-adding stage directly and through said first-frequency divider in order that the divided frequency and input frequency are added, and a second-converting circuit including a second-frequency divider and a pulse-subtracting stage, the output of said pulse-adding stage being connected directly and through said frequency divider of the secondconverting circuit to said pulse-subtracting stage for subtracting the output frequency from said second-frequency divider from the output frequency from said first-frequency divider, the output frequency from said second-converting circuit being a frequency corresponding to sidereal time.
Claim 2
Dependent Claim
139 words
An electronic frequency converter for transforming a frequency corresponding to mean time time into a frequency corresponding to sidereal time, comprising an input circuit for producing a pulse series at an input frequency corresponding to mean time, a first-converting circuit including a first-frequency divider and a pulse-adding stage, said input circuit being connected to said pulse-adding stage directly and through said first-frequency divider in order that the divided frequency and input frequency are added, and a second-converting circuit including a second-frequency divider and a pulse-subtracting stage, the output of said pulse-adding stage being connected directly and through said frequency divider of the secondconverting circuit to said pulse-subtracting stage for subtracting the output frequency from said second-frequency divider from the output frequency from said first-frequency divider, the output frequency from said second-converting circuit being a frequency corresponding to sidereal time.
Claim 3
Dependent Claim
32 words
A converter according to claim 1, wherein said first-converting circuit has a first-frequency divider with a ratio of 1:365 and said second-converting circuit has a second-frequency divider with a ratio of 1:551,950.
Claim 4
Dependent Claim
21 words
A converter according to claim 1, comprising means for shifting the pulses fed to said pulse-adding stage from said first-frequency divider.
Claim 5
Dependent Claim
15 words
A converter according to claim 3, comprising a shifting stage series-connected with the first-frequency divider.
Claim 6
Dependent Claim
14 words
A converter according to claim 1, wherein said pulse-adding stage is an NOR gate.
Claim 7
Dependent Claim
14 words
A converter according to claim 1, wherein said pulse-subtracting stage is a NAND gate.
Claim 8
Dependent Claim
29 words
A converter according to claim 1, wherein said second-converting circuit which includes a pulse-subtracting stage has an input flip-flop memory circuit adapted to be reset by the output pulses.
Claim 9
Dependent Claim
38 words
A converter according to claim 7, wherein a NOR gate is connected into the input of said second-frequency divider and the outputs of the flip-flop memory circuit and of the second-frequency divider are connected to a NAND gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-20 | 1975-06-21 | 1975-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-20 | 1979-06-21 | 1979-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-20 | 1983-06-21 | 1983-12-21 | $7700.00 | Window Closed / Lapsed |