Patent US3629503A successfully refreshed from Google Patents.
US3629503A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital synchronization system
Assignee: RCA Corp
•
Filing: 1969-04-01
•
Granted: 1971-12-21
•
Expires: 1989-04-01
Abstract
Abstract A system for automatically adjusting a receiver to the ''''format'''' of received characters. The format refers to the number B of bit transmission intervals per character and the duration Delta t of each such interval, where B is unknown and is in the range BO to Bm and Delta t is unknown and is in the range Delta tO to Delta tm. In response to the reception of timing signals of duration BO Delta t, where only BO is known in advance, the system generates clock pulses spaced intervals Delta t. In the response to the reception of timing signals of duration B Delta t, after Delta t has been ascertained by the system, it generates B such clock pulses for each subsequently received character, each clock pulse concurrent with a character bit interval.
Inventors
- 👤 Lawrence A Rempert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:49
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A system for producing one clock pulse per bit of successive, serially transmitted characters, where each character transmission interval includes a duration B Delta t during which intelligence is transmitted, where B, which may be unknown, is the number of bit intervals and is in the range B0 to Bm and where Delta t, which also may be unknown, is some value in the range Delta t0 to Delta tm comprising, in combination: means for transmitting timing signals, each of duration B0 Delta t, where B0 is known in advance; means receptive of said timing signals for producing clock pulses at intervals Delta t; means for transmitting a timing signal of duration B Delta t after said clock pulses are produced at intervals Delta t; and means receptive of said last-named timing signal for producing, during each succeeding character transmission interval, B clock pulses, each concurrent with a bit interval of a character.
Claim 2
Independent Claim
153 words
A system for producing one clock pulse per bit of successive, serially transmitted characters, where each character transmission interval includes a duration B Delta t during which intelligence is transmitted, where B, which may be unknown, is the number of bit intervals and is in the range B0 to Bm and where Delta t, which also may be unknown, is some value in the range Delta t0 to Delta tm comprising, in combination: means for transmitting timing signals, each of duration B0 Delta t, where B0 is known in advance; means receptive of said timing signals for producing clock pulses at intervals Delta t; means for transmitting a timing signal of duration B Delta t after said clock pulses are produced at intervals Delta t; and means receptive of said last-named timing signal for producing, during each succeeding character transmission interval, B clock pulses, each concurrent with a bit interval of a character.
Claim 3
Dependent Claim
84 words
In a system as set forth in claim 1, said means for producing clock pulses at intervals Delta t including: first, second, and third counters; a fixed frequency oscillator supplying pulses to be counted to the first counter; means for producing an output when the counts in the first and second counters are equal and applying that output to the third counter; and means for advancing by one the count stored on the second counter each time the third counter reaches a given count.
Claim 4
Dependent Claim
75 words
In a system as set forth in claim 1, said last-named means including: first and second counting means; means producing pulses at intervals Delta t and applying them to said first couNting means; means for stopping said first counting means when it has counted B such pulses; and means for thereafter applying said pulses to said second counting means, and for resetting the same each time the counts in the two counting means are equal.
Claim 5
Dependent Claim
23 words
A system as set forth in claim 1, further including: means for suppressing one clock pulse in each group of B clock pulses.
Claim 6
Dependent Claim
195 words
In a circuit for producing clock pulses at a frequency which is synchronous with that of received timing pulses, in combination: an oscillator for producing signals at a frequency substantially higher than the repetition frequency of said timing pulses; first counter means responsive to received timing pulses for counting, during the interval of each such timing pulse, the signals produced by said oscillator; first count-indicating means for both resetting said first counter means and for producing an output signal X each time, during the interval of a timing pulse, said first counter means reaches a given count; second counter means for counting, during the interval of each timing pulse; said output signals X; second count-indicating means for both resetting said second counter means and for producing an output signal Y each time, during the interval of a timing pulse, said second counter means reaches a predetermined count; means responsive to each second output signal Y for increasing by one the count to which said first count indicating means is responsive; and means for indicating when said last-named means ceases to produce at least one output signal Y during the interval of a received timing pulse.
Claim 7
Dependent Claim
195 words
In a circuit for producing clock pulses at a frequency which is synchronous with that of received timing pulses, in combination: an oscillator for producing signals at a frequency substantially higher than the repetition frequency of said timing pulses; first counter means responsive to received timing pulses for counting, during the interval of each such timing pulse, the signals produced by said oscillator; first count-indicating means for both resetting said first counter means and for producing an output signal X each time, during the interval of a timing pulse, said first counter means reaches a given count; second counter means for counting, during the interval of each timing pulse; said output signals X; second count-indicating means for both resetting said second counter means and for producing an output signal Y each time, during the interval of a timing pulse, said second counter means reaches a predetermined count; means responsive to each second output signal Y for increasing by one the count to which said first count indicating means is responsive; and means for indicating when said last-named means ceases to produce at least one output signal Y during the interval of a received timing pulse.
Claim 8
Dependent Claim
34 words
In a circuit as set forth in claim 5, said first count-indicating means including a third counter means and means for comparing the count stored therein with the count of said first counting means.
Claim 9
Dependent Claim
40 words
In a circuit as set forth in claim 5, further including a frequency divider receptive of said pulses X for producing n pulses each timing pulse interval, where n is the number of bit intervals within said timing pulse interval.
Claim 10
Dependent Claim
30 words
In a circuit as set forth in claim 5, said last-named means comprising a flip-flop coupled to said second count-indicating means and means for sensing the state of said flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-20 | 1975-06-21 | 1975-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-20 | 1979-06-21 | 1979-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-20 | 1983-06-21 | 1983-12-21 | $7700.00 | Window Closed / Lapsed |