Patent US3628067A successfully refreshed from Google Patents.
US3628067A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low power current pulser for inductive loads
Assignee: Collins Radio Co
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Filing: 1969-10-31
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Granted: 1971-12-14
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Expires: 1989-10-31
Abstract
Abstract A core driving circuit, particularly useful for submicrosecond computer memories, designed for minimum power loss with switching in the output stage from a relatively high-source voltage through the rise times to a much lower source voltage through the flat top portions of regulated output current pulses.
Inventors
- 👤 Charles P Womack
- 👤 Charles J Ulrick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:34
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/64; G; G11; G11C; G11C11/00; G11C11/02; G11C11/06; G11C11/06007
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
150 words
In an inductive load driving circuit subject to being fed activating voltage pulsed signal inputs: signal input connective means; inductive load connective means; relatively high-voltage source means; relatively low-voltage source means; a first circuit path with opening and closing control means connected to said relatively high-voltage source; a second circuit path with opening and closing control means connected to said relatively low-voltage source; differential DC voltage value sensing means including a current sense resistor, and resistive means in a signal input to output load circuit path from said signal input connective means; and said differential DC voltage value sensing means having control signal connections to the control means of both of said first and second circuit paths and including: resistive network means; and differential voltage value sensing means connected across two junctions of said resistive network means; and wherein said differential DC voltage value sensing means is a differential amplifier.
Claim 2
Dependent Claim
150 words
In an inductive load driving circuit subject to being fed activating voltage pulsed signal inputs: signal input connective means; inductive load connective means; relatively high-voltage source means; relatively low-voltage source means; a first circuit path with opening and closing control means connected to said relatively high-voltage source; a second circuit path with opening and closing control means connected to said relatively low-voltage source; differential DC voltage value sensing means including a current sense resistor, and resistive means in a signal input to output load circuit path from said signal input connective means; and said differential DC voltage value sensing means having control signal connections to the control means of both of said first and second circuit paths and including: resistive network means; and differential voltage value sensing means connected across two junctions of said resistive network means; and wherein said differential DC voltage value sensing means is a differential amplifier.
Claim 3
Dependent Claim
62 words
The inductive load driving circuit of claim 1, wherein said differential amplifier includes at least two solid state active devices each having at least three electrodes; with one electrode interconnected with a like electrode between two of said solid state active devices; and with the interconnection between electrodes connected through a maximum flow limit current source to a voltage potential reference source.
Claim 4
Dependent Claim
22 words
The inductive load driving circuit of claim 2, wherein said solid state active devices are transistors, and the interconnected electrodes are emitters.
Claim 5
Dependent Claim
131 words
The inductive load driving circuit of claim 3, wherein a circuit from the input to the output load connection includes a first resistor and a second resistor; with the base of a first transistor of said differential amplifier connected to the junction of said first and second resistors; a sense resistor; and third and fourth resistors connected in series with the sense resistor from the circuit output inductive load connection through said third and fourth resistors to said voltage potential reference source; power supply circuit means including said first and seCond circuit paths having a common single connection to the junction of said sense resistor and said third resistor; and with the base of a second transistor of said differential amplifier connected to the junction of said third and fourth resistors.
Claim 6
Dependent Claim
58 words
The inductive load driving circuit of claim 4, wherein said sense resistor is a relatively small value resistor; said second and third resistors are substantially equal value of a much greater magnitude than with said sense resistor; and with said first and fourth resistors of substantially equal value and of greater value than said second and third resistors.
Claim 7
Dependent Claim
96 words
The inductive load driving circuit of claim 4, wherein the control signal connection to the control means of both said first and second circuit paths is from the collector of said first transistor of the differential amplifier to the base of a first-type transistor having an emitter connection to the base of a transistor of the same first-type with the emitter collector junction thereof in said first circuit path; and with the collector of said first-type transistor connected to the base of a second-type transistor with the emitter collector junction thereof in said second circuit path.
Claim 8
Dependent Claim
25 words
The inductive load driving circuit of claim 6, wherein unidirectional current flow means is included in said second circuit path from said relatively low-voltage source.
Claim 9
Dependent Claim
50 words
The inductive load driving circuit of claim 7, wherein circuit bias means is provided for the transistors; said first-type transistors are PNP transistors; said second-type transistors are NPN transistors; said voltage sources are positive voltage sources and said unidirectional current flow means is the emitter collector junction through a transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-13 | 1975-06-14 | 1975-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-13 | 1979-06-14 | 1979-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-13 | 1983-06-14 | 1983-12-14 | $7700.00 | Window Closed / Lapsed |