Computer system event counter

Claim 1

An event counter network comprising, in combination: a plurality of counterstages joined in tandem, a first of said stages responding to each input signal and each succeeding stage responding to every tenth signal received by the preceding stage, each of the counterstages including a binary code decimal counter responding to binary input signals and providing a binary code decimal signal output and decoder means for decoding the binary code decimal signal and generating responsive decimal digit signals, each binary code decimal counter having four output points having binary weights 1, 2, 4and 8, respectively, each of the decoder means receiving the signals of its associated output points and providing responsive decimal digit signals of 0-9, the input of each of the binary code decimal counters succeeding the first binary code decimal counter being connected to the output point having a binary weight 8 of the binary code decimal counter of the preceding stage, each of said succeeding binary code decimal counters being responsive to a binary input from a binary ''''1'''' to a binary ''''0,'''' hold means for holding the responsive decimal digit signals of the succeeding stages intermediate receipt of responsive input signals, indicator tube banks responsive to the decimal digit signals and indicating a decimal digit responsive to said decimal digit signals, each of said indicator tube banks providing a decimal digit 0-9 responsive to said decimal digit signals; an overflow network responsive to the last of said counter stages for generating an overflow indication after said last stage records a decimal ''''9,'''' reset means for resetting all of said counter stages to decimal digit ''''0;'''' and delay means for temporarily interrupting the count of said network while simultaneously receiving input signals.