Patent US3627946A successfully refreshed from Google Patents.
US3627946A
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Method and apparatus for encoding asynchronous digital signals
Assignee: NTT Inc
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Filing: 1969-07-08
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Granted: 1971-12-14
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Expires: 1989-07-08
Abstract
Abstract In transmitting a digital signal, e.g. a digital signal on a PCM transmission line which is asynchronous with a clock signal, a first and a second state pulse trains respectively corresponding to one of the binary states of the digital signal are utilized and the output pulse trains of the asynchronous digital signal are represented by corresponding mode pulse trains in respective time slots. When the state of the pulse train of the asynchronous digital signal changes an indicating pulse representing the time of transition of the state of the asynchronous digital signal is inserted in a time slot following the time slot in which the state has changed. On the receiving terminal the mode pulse trains are constructed by utilizing the framing pulse as the reference signal.
Inventors
- 👤 Nobuo Inoue
- 👤 Yuichi Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:31
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/493; H04J; H04J3/00; H04J3/02; H04J3/06; H04L5/00; H04L5/22; H04L5/225; H04L5/24
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
203 words
In a clocked PCM data transmission system for transmitting asynchronous digital signals, said system being of the type having means for sampling said signals for transitions of the state of said signals and upon detecting a transition transmitting at the next clock pulse a pulse representing said transition and at the next successive clock pulse transmitting a pulse representing a time region in which said transition occurred within the clock pulse interval, the improved method comprising: developing a mode pulse train consisting of alternate ONES and ZEROS at the clock interval to represent one state of the data signal with the other state of the data signal represented by the logical NOT of said mode pulse train; transmitting said mode pulse train to represent one state of said data signal in the absence of a transition in said data signal; sampling said data signal at clock rate to detect said transitions and obtain a data-clocked pulse train representing said data signal; combining by exclusive OR logic said mode pulse train and said data-clocked pulse train to alter the transmitted pulse train in accordance with said exclusive OR output except for said next successive pulse to represent the other state of said data signal.
Claim 2
Dependent Claim
203 words
In a clocked PCM data transmission system for transmitting asynchronous digital signals, said system being of the type having means for sampling said signals for transitions of the state of said signals and upon detecting a transition transmitting at the next clock pulse a pulse representing said transition and at the next successive clock pulse transmitting a pulse representing a time region in which said transition occurred within the clock pulse interval, the improved method comprising: developing a mode pulse train consisting of alternate ONES and ZEROS at the clock interval to represent one state of the data signal with the other state of the data signal represented by the logical NOT of said mode pulse train; transmitting said mode pulse train to represent one state of said data signal in the absence of a transition in said data signal; sampling said data signal at clock rate to detect said transitions and obtain a data-clocked pulse train representing said data signal; combining by exclusive OR logic said mode pulse train and said data-clocked pulse train to alter the transmitted pulse train in accordance with said exclusive OR output except for said next successive pulse to represent the other state of said data signal.
Claim 3
Dependent Claim
196 words
In apparatus for encoding an asynchronous digital signal characterized by having means to generate a clock pulse, means to sample said asynchronous digital signal with the clock pulse from the clock pulse generating means to produce sampled data pulses, means to divide said clock pulse for generating a framing pulse, and means for providing after a first sampled data pulse in the next clock pulse time following a transition a coded region pulse in the next successive clock pulse time representing a predetermined divided region of a time slot interval in which tHe state of said asynchronous digital signal changed, the improvement comprising: means responsive to said framing pulse and said clock pulse to generate a mode pulse train consisting of alternate ONES and ZEROS or vice versa corresponding to either 1 or 0 state, an encoding means supplied with said mode pulse train and said sampled data pulses, said encoding means operating to combine the signals supplied thereto in exclusive OR logic to produce one of said corresponding mode pulse trains in accordance with the state of said asynchronous digital signal, and means to insert said framing pulse into the output from said encoding means.
Claim 4
Dependent Claim
196 words
In apparatus for encoding an asynchronous digital signal characterized by having means to generate a clock pulse, means to sample said asynchronous digital signal with the clock pulse from the clock pulse generating means to produce sampled data pulses, means to divide said clock pulse for generating a framing pulse, and means for providing after a first sampled data pulse in the next clock pulse time following a transition a coded region pulse in the next successive clock pulse time representing a predetermined divided region of a time slot interval in which tHe state of said asynchronous digital signal changed, the improvement comprising: means responsive to said framing pulse and said clock pulse to generate a mode pulse train consisting of alternate ONES and ZEROS or vice versa corresponding to either 1 or 0 state, an encoding means supplied with said mode pulse train and said sampled data pulses, said encoding means operating to combine the signals supplied thereto in exclusive OR logic to produce one of said corresponding mode pulse trains in accordance with the state of said asynchronous digital signal, and means to insert said framing pulse into the output from said encoding means.
Claim 5
Dependent Claim
93 words
Apparatus for encoding and multiplexing m-channel asynchronous digital signals characterized by apparatus according to claim 2 for each of said channels, said clock pulse generating means being common to all channels and further comprising means responsive to said clock pulse to generate m channel pulses, means to sample the asynchronous digital signals in each channel in response to each channel pulse generated by said channel pulse generating means, and multiplexing means to multiplex all outputs from said encoding means into a multiplex pulse train each frame consisting of two bits of m channels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-13 | 1975-06-14 | 1975-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-13 | 1979-06-14 | 1979-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-13 | 1983-06-14 | 1983-12-14 | $7700.00 | Window Closed / Lapsed |