Counting system for measuring a difference between frequencies of two signals

Claim 2

A counting system for measuring a difference between respective frequencies of a first input signal A and a second input signal B, comprising: a signal converter converting said signals A and B respectively to a first pulse train Aa whose pulses are each timed with each of the cycles of the first input signal and to a second pulse train Ba whose pulses are each timed with each of the cycles of the second input signal B; said signal converter comprising a first pulse generator receiving the first input signal A to generate a first setting pulse in response to each cycle of the first input signal A, a second pulse generator receiving the second input signal B to generate a second setting pulse in response to each cycle of the second input signal B, an OR circuit having two inputs connected respectively to outputs of the first and second pulse generators, a clock pulse generator connected to the output of the OR circuit to generate clock pulses each having a constant duration and timed with the end of each of the output pulses of the OR circuit, a NOT circuit connected to the output of the clock pulse generator, a first AND circuit having two inputs respectively connected to outputs of the first signal generator and the NOT circuit, a second AND circuit having two inputs respectively connected to outputs of the second pulse generator and the NOT circuit, a first bistable circuit set by the output pulse of the first AND circuit and reset by the output of the NOT circuit, and a second bistable circuit set by the output of the second AND circuit and reset by the output of the NOT circuit, the first pulse train Aa being obtained at the output of the first bistable circuit, the second pulse train Ba being obtained at the output of the second bistable circuit, a sequential logical circuit connected in cascade with the signal converter and having three possible states to generate an output pulse in response to every received pulse of at least one of the first pulse train Aa and the second pulse train Ba in a predetermined condition which is predetermined in accordance with the instant state of this sequential logical circuit and the instant states of the first pulse train Aa and the second pulse train Ba, so that the sequential logical circuit assuming a first state when a difference number between the respective numberS of received pulses of the first and second pulse trains Aa and Ba is equal to the number of generated output pulse or pulses, a second state when the difference number is larger than the number of generated output pulse or pulses and when the number of received pulses of the first pulse train Aa is larger than the number of received pulses of the second pulse train Ba, and a third state when the difference is larger than the number of generated output pulse or pulses and when the number of received pulses of the first pulse train Aa is smaller than the number of received pulses of the second pulse train Ba; and a counter connected to the output of the sequential logical circuit to count the number of output pulses of the sequential logical circuit in a desired time.

Claim 3

A counting system according to claim 1, in which the sequential logical circuit comprises a first input terminal receiving a first pulse signal obtained by inverting the state of the first pulse train Aa, a second input terminal receiving a second pulse signal obtained by inverting the state of the second pulse train Ba, a third input terminal receiving clock pulses each of which is synchronized with the end of each of pulses obtained by the logical OR of the first pulse train and the second pulse train, a third AND circuit having two inputs one of which is connected to the second input terminal, a fourth AND circuit having two inputs one of which is connected to the first input terminal, a third bistable circuit set by the output of the third AND circuit and reset by the first pulse signal applied from the first input terminal, a fourth bistable circuit set by the output of the fourth AND circuit and reset by the second pulse signal applied from the second input terminal, a fifth AND circuit having three inputs connected respectively to the second input terminal, one output of the third bistable circuit and the third input terminal, a sixth AND circuit having three inputs connected respectively to the first input terminal, one output of the fourth bistable circuit and the third input terminal, the other output of the third bistable circuit being connected to the other input of the fourth AND circuit, the other output of the fourth bistable circuit being connected to the other input of the third AND circuit, and a second OR circuit having two inputs respectively connected to the outputs of the fifth AND circuit and the sixth AND circuit, the output pulses the sequential logical circuit being obtained at the output of the second OR circuit.

Claim 4

A counting system for measuring a difference between respective frequencies of the first input signal A and the second input signal B, comprising: a signal converter converting said signals A and B to a first pulse train Aa whose pulses are each timed with each of the cycles of the first input signal and to a second pulse train Ba whose pulses are each timed with each of the cycles of the second input signal B; said signal converter comprising first and second pulse generators receiving said input signals A and B respectively, an OR circuit connected to the outputs of both said pulse generators, a clock pulse generator connected to the output of said OR circuit, and means connected to the outputs of said pulse generator and said clock pulse generator for producing said pulse trains Aa and Ba respectively, a sequential logical circuit connected in cascade with the signal converter and having three possible states to generate an output pulse in response to every received pulse of at least one of the first pulse train Aa and the second pulse train Ba in a predetermined condition which is predetermined in accordance with the instant state of this sequential logical circuit and the instant states of the first pulse train Aa and the second pulse train Ba, so that the sequential logical ciRcuit assuming a first state when a difference number between the respective numbers of received pulses of the first and second pulse trains Aa and Ba is equal to the number of generated output pulse or pulses, a second state when the difference number is larger than the number of generated output pulse or pulses and when the number of received pulses of the first pulse train Aa is larger than the number of received pulses of the second pulse train Ba, and a third state when the difference is larger than the number of generated output pulse or pulses and when the number of received pulses of the first pulse train Aa is smaller than the number of received pulses of the second pulse train Ba; and said sequential logical circuit comprising a first input terminal receiving from said signal converter a first pulse signal obtained by inverting the state of the first pulse train Aa, a second input terminal receiving from said signal converter a second pulse signal obtained by inverting the state of the second pulse train Ba, a third input terminal receiving clock pulses from said clock pulse generator each of which is synchronized with the end of each of pulses obtained by the logical OR of the first pulse train and the second pulse train, a first AND circuit having two inputs one of which is connected to the second input terminal, a second AND circuit having two inputs one of which is connected to the first input terminal, a first bistable circuit set by the output of the first AND circuit and reset by the first pulse signal applied from the first input terminal, a second bistable circuit set by the output of the second AND circuit and reset by the second pulse signal applied from the second input terminal, a third AND circuit having three inputs connected respectively to the second input terminal, one output of the first bistable circuit and the third input terminal, a fourth AND circuit having three inputs connected respectively to the first input terminal, one output of the second bistable circuit and the third input terminal, the other output of the first bistable circuit being connected to the other input of the second AND circuit, the other output of the second bistable circuit being connected to the other input of the first AND circuit, and a second OR circuit having two inputs respectively connected to the outputs of the third AND circuit and the fourth AND circuit, the output pulses the sequential logical circuit being obtained at the output of the second OR circuit, a counter connected to the output of the sequential logical circuit to count the number of output pulses of the sequential logical circuit in a desired time.

Claim 5

A counting system for measuring a difference between respective frequencies of the first input signal A and the second input signal B, comprising: a signal converter converting said signals A and B to a first pulse train Aa whose pulses are each timed with each of the cycles of the first input signal and to a second pulse train Ba whose pulses are each timed with each of the cycles of the second input signal B; said signal converter comprising first and second pulse generators receiving said input signals A and B respectively, an OR circuit connected to the outputs of both said pulse generators, a clock pulse generator connected to the output of said OR circuit, and means connected to the outputs of said pulse generator and said clock pulse generator for producing said pulse trains Aa and Ba respectively, a sequential logical circuit connected in cascade with the signal converter and having three possible states to generate an output pulse in response to every received pulse of at least one of the first pulse train Aa and the second pulse train Ba in a predetermined condition which is predetermined in accordance with the instant state of this sequential logical circuit and the instant states of the first pulse train Aa and the second pulse train Ba, so that the sequential logical ciRcuit assuming a first state when a difference number between the respective numbers of received pulses of the first and second pulse trains Aa and Ba is equal to the number of generated output pulse or pulses, a second state when the difference number is larger than the number of generated output pulse or pulses and when the number of received pulses of the first pulse train Aa is larger than the number of received pulses of the second pulse train Ba, and a third state when the difference is larger than the number of generated output pulse or pulses and when the number of received pulses of the first pulse train Aa is smaller than the number of received pulses of the second pulse train Ba; and said sequential logical circuit comprising a first input terminal receiving from said signal converter a first pulse signal obtained by inverting the state of the first pulse train Aa, a second input terminal receiving from said signal converter a second pulse signal obtained by inverting the state of the second pulse train Ba, a third input terminal receiving clock pulses from said clock pulse generator each of which is synchronized with the end of each of pulses obtained by the logical OR of the first pulse train and the second pulse train, a first AND circuit having two inputs one of which is connected to the second input terminal, a second AND circuit having two inputs one of which is connected to the first input terminal, a first bistable circuit set by the output of the first AND circuit and reset by the first pulse signal applied from the first input terminal, a second bistable circuit set by the output of the second AND circuit and reset by the second pulse signal applied from the second input terminal, a third AND circuit having three inputs connected respectively to the second input terminal, one output of the first bistable circuit and the third input terminal, a fourth AND circuit having three inputs connected respectively to the first input terminal, one output of the second bistable circuit and the third input terminal, the other output of the first bistable circuit being connected to the other input of the second AND circuit, the other output of the second bistable circuit being connected to the other input of the first AND circuit, and a second OR circuit having two inputs respectively connected to the outputs of the third AND circuit and the fourth AND circuit, the output pulses the sequential logical circuit being obtained at the output of the second OR circuit, a counter connected to the output of the sequential logical circuit to count the number of output pulses of the sequential logical circuit in a desired time.