Two terminal current regulator

Claim 2

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having base, collector and emitter electrodes; means connecting said first device emitter electrode to said first terminal; means connecting said first device collector electrode to said second terminal; biasing means connecting said first device base electrode to said second terminal; means connecting said second device emitter electrode to said first terminal; means connecting said second device collector electrode to said first semiconductor base electrode; and means coupling a portion of a variable direct voltage developed across said first and second terminals to said second device base electrode whereby increased conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 3

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having a base, a collector and an emitter; a resistor connected between said first device emitter and said first terminal; said first device collector being connected to said second terminal; biasing means connecting said first device base to said second terminal; said second device emitter being connected to the first terminal; means connecting said second device collector to said first device base; and means coupling a portion of a variable direct voltage developed across said first and second terminals to said second device base whereby increased conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 4

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having a base, a collector and an emitter; a resistor connected between said first device emitter and said first terminal; said first device collector being connected to said second terminal; biasing means connecting said first device base to said second terminal; said second device emitter being connected to the first terminal; means connecting said second device collector to said first device base; and means coupling a portion of a variable direct voltage developed across said first and second terminals to said second device base whereby increased conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 5

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having base, collector and emitter electrodes; means connecting said first device emitter electrode to said first terminal; means connecting said first device collector electrode to said second terminal; biasing means connecting said first device base electrode to said second terminal; means connecting said second device emitter electrode to said first terminal; means connecting said second device collector electrode to said first device base electrode; a voltage divider coupled to said first and second terminals and across which a variable direct voltage is developed; and means coupling said voltage divider to said second device base whereby increased conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 6

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having base, collector and emitter electrodes; means connecting said first device emitter electrode to said first terminal; means connecting said first device collector electrode to said second terminal; biasing means connecting said first device base electrode to said second terminal; means connecting said second device emitter electrode to said first terminal; means connecting said second device collector electrode to said first device base electrode; a voltage divider coupled to said first and second terminals and across which a variable direct voltage is developed; and means coupling said voltage divider to said second device base whereby increased conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 7

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having a base, a collector and an emitter; said first device emitter being connected to said first terminal; said first device collector being connected to said second terminal; biasing means connecting said first device base to said second terminal; said second device emitter being connected to said first terminal; means coupling said second device collector to said first device base; a voltage divider coupled to said first and second terminals and across which a variable direct voltage is developed; and means coupling a diode to said voltage divider and said second device base increased whereby conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 8

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having a base, a collector and an emitter; said first device emitter being connected to said first terminal; said first device collector being connected to said second terminal; biasing means connecting said first device base to said second terminal; said second device emitter being connected to said first terminal; means coupling said second device collector to said first device base; a voltage divider coupled to said first and second terminals and across which a variable direct voltage is developed; and means coupling a diode to said voltage divider and said second device base increased whereby conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 9

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having a base, a collector and an emitter; an impedance element coupled between said first device emitter and said first terminal; said first device collector being coupled to said second terminal; biasing means Coupling said base of said first device to said second terminal; said second device emitter being coupled to said first terminal; coupling means coupling said second device collector to said first device base; a voltage divider coupled to said first and second terminals and across which a variable direct voltage is developed; and means coupling said voltage divider to said second device base whereby increased conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 10

A two-terminal network comprising: first and second terminals; first and second semiconductor devices each having a base, a collector and an emitter; an impedance element coupled between said first device emitter and said first terminal; said first device collector being coupled to said second terminal; biasing means Coupling said base of said first device to said second terminal; said second device emitter being coupled to said first terminal; coupling means coupling said second device collector to said first device base; a voltage divider coupled to said first and second terminals and across which a variable direct voltage is developed; and means coupling said voltage divider to said second device base whereby increased conduction of said second device in response to an increased voltage across said first and second terminals renders said first device less conductive.

Claim 11

A two-terminal network comprising: first and second terminals across which a variable direct voltage is developed; first and second semiconductor devices each having a base, collector and emitter; means connecting said first device emitter to said first terminal; means connecting said first device collector to said second terminal; biasing means coupled to said first device base for biasing said first device into saturation; means coupling said second device emitter to said first terminal; means coupling said second device collector to said first device base; and means coupling a portion of the voltage developed across said first and second terminals to said second device base so that as said voltage developed across said first and second terminals increases beyond a predetermined level said second device is rendered conductive and renders said first device nonconductive.

Claim 12

A two-terminal network comprising: first and second terminals across which a variable direct voltage is developed; first and second semiconductor devices each having a base, collector and emitter; means connecting said first device emitter to said first terminal; means connecting said first device collector to said second terminal; biasing means coupled to said first device base for biasing said first device into saturation; means coupling said second device emitter to said first terminal; means coupling said second device collector to said first device base; and means coupling a portion of the voltage developed across said first and second terminals to said second device base so that as said voltage developed across said first and second terminals increases beyond a predetermined level said second device is rendered conductive and renders said first device nonconductive.

Claim 13

A two-terminal network comprising: first and second terminals across which a variable direct voltage is developed; first and second semiconductor device each having a base, collector and emitter; means connecting said first device emitter to said first terminal; means connecting said first device collector to said second terminal; biasing means coupled to said first device base for biasing said first device into saturation; means connecting said second device emitter to said first terminal; means connecting said second device collector to said first device biasing means; means biasing said second device to cutoff, said second device biasing means coupling a portion of the voltage developed across said first and second terminals to said second device base, so that as said voltage developed across said first and second terminals reaches a predetermined level said second device switches into a saturated condition cutting off said first device.

Claim 14

A two-terminal network comprising: first and second terminals across which a variable direct voltage is developed; first and second semiconductor device each having a base, collector and emitter; means connecting said first device emitter to said first terminal; means connecting said first device collector to said second terminal; biasing means coupled to said first device base for biasing said first device into saturation; means connecting said second device emitter to said first terminal; means connecting said second device collector to said first device biasing means; means biasing said second device to cutoff, said second device biasing means coupling a portion of the voltage developed across said first and second terminals to said second device base, so that as said voltage developed across said first and second terminals reaches a predetermined level said second device switches into a saturated condition cutting off said first device.

Claim 15

A two-terminal network comprising: first and second terminals across which a variable direct voltage is developed; first and second semiconductor devices each having a base, collector and emitter; means coupling said first device emitter to said first terminal; means coupling said first device collector to said second terminal; biasing means coupled to said first device base for biasing said first device into saturation; means coupling said second device emitter to said first terminal; means coupling the second device collector to said first device base; biasing means biasing said second device to cutoff, said second device biasing means coupling a portion of the voltage developed across said first and second terminal to said second device base, so that when said voltage developed across said first and second terminals reaches a predetermined level said second device switches into a saturated condition cutting off said first device, whereby said second device remains in a saturated condition and said first device remains cutoff until the current to the two-terminal network is cut off.

Claim 16

A two-terminal network comprising: first and second terminals across which a variable direct voltage is developed; first and second semiconductor devices each having a base, collector and emitter; means coupling said first device emitter to said first terminal; means coupling said first device collector to said second terminal; biasing means coupled to said first device base for biasing said first device into saturation; means coupling said second device emitter to said first terminal; means coupling the second device collector to said first device base; biasing means biasing said second device to cutoff, said second device biasing means coupling a portion of the voltage developed across said first and second terminal to said second device base, so that when said voltage developed across said first and second terminals reaches a predetermined level said second device switches into a saturated condition cutting off said first device, whereby said second device remains in a saturated condition and said first device remains cutoff until the current to the two-terminal network is cut off.

Claim 17

A current limiting device comprising: first and second terminals across which a variable direct voltage is developed; first and second transistors each having a base, collector and emitter; a first resistor connected between said first terminal and said first transistor emitter; said first transistor collector being connected to said second terminal; said second transistor emitter being connected to said first terminal; said second transistor collector being connected to said first transistor base; a second resistor connected between said first transistor base and said second terminal; third and fourth resistors connected together forming a junction, said third and fourth resistors being connected between said first and second terminals; and a diode coupled between the junction of said third and fourth resistors and said second transistor base.

Claim 18

A current limiting device comprising: first and second terminals across which a variable direct voltage is developed; first and second transistors each having a base, collector and emitter; a first resistor connected between said first terminal and said first transistor emitter; said first transistor collector being connected to said second terminal; said second transistor emitter being connected to said first terminal; said second transistor collector being connected to said first transistor base; a second resistor connected between said first transistor base and said second terminal; third and fourth resistors connected together forming a junction, said third and fourth resistors being connected between said first and second terminals; and a diode coupled between the junction of said third and fourth resistors and said second transistor base.

Claim 19

A current-limiting device comprising: first and second terminals across which a variable direct voltage is developed; first and second transistors each having a base, collector and emitter; first resistor one lead of which is coupled to said first terminal and the other lead of which is coupled to said emitter of said first transistor; said collector of said first transistor being coupled to said second terminal; said emitter of said second transistor being connected to said first terminal; said collector of said second transistor being coupled to said first transistor base; a second resistor one lead of which is coupled to said first transistor base and the other lead of which is coupled to said second terminal; a voltage divider coupled across said first and second terminals; and means coupling said voltage divider to said second transistor base.

Claim 20

A current-limiting device comprising: first and second terminals across which a variable direct voltage is developed; first and second transistors each having a base, collector and emitter; first resistor one lead of which is coupled to said first terminal and the other lead of which is coupled to said emitter of said first transistor; said collector of said first transistor being coupled to said second terminal; said emitter of said second transistor being connected to said first terminal; said collector of said second transistor being coupled to said first transistor base; a second resistor one lead of which is coupled to said first transistor base and the other lead of which is coupled to said second terminal; a voltage divider coupled across said first and second terminals; and means coupling said voltage divider to said second transistor base.

Claim 21

An electric circuit for use with a two-terminal direct current source and a two-terminal load, where a first load terminal is connected to a first source terminal and where said circuit is connected between the second load terminal and the second source terminal, across which a variable direct voltage is developed, a transistor having emitter, base and collector electrodes; a resistor connected between one of said second load terminal and said second source terminal and said transistor emitter electrode; said collector electrode being connected to the other of said second load terminal and said second source terminal; means coupled to said base electrode for biasing said transistor into saturation; and means operable to couple a portion of the voltage developed between said second load and source terminals at a predetermined current to said transistor base electrode to cutoff said transistor.

Claim 22

An electric circuit for use with a two-terminal direct current source and a two-terminal load, where a first load terminal is connected to a first source terminal and where said circuit is connected between the second load terminal and the second source terminal, across which a variable direct voltage is developed, a transistor having emitter, base and collector electrodes; a resistor connected between one of said second load terminal and said second source terminal and said transistor emitter electrode; said collector electrode being connected to the other of said second load terminal and said second source terminal; means coupled to said base electrode for biasing said transistor into saturation; and means operable to couple a portion of the voltage developed between said second load and source terminals at a predetermined current to said transistor base electrode to cutoff said transistor.

Claim 23

An electric circuit for use with a two-terminal direct current source and a two-terminal load where a first load terminal is connected to a first source terminal and where said circuit is connected between the second source terminal and the second load terminal across which a variable direct voltage is developed said electric circuit comprising: a first transistor having emitter, base and collector electrodes; said emitter and collector electrodes being respectively connected to said second source terminal and said second load terminal; biasing means coupled to said base electrode for biasing said first transistor into saturation; a second transistor having emitter, base, and collector electrodes; said second transistor emitter electrode being connected to said first transistor emitter electrode; said second transistor collector electrode being connected to said biasing means; biasing means coupled to said second transistor base electrode for biasing said second transistor to cutoff; said second transistor biasing means coupling a portion of the voltage developed across said second source terminal and second load terminal to said second transistor base electrode whereby at a predetermined level said voltage switches said second transistor into saturation and said first transistor into cutoff, said circuit remaining in this condition until the current flow between said current source and said load is cutoff.

Claim 24

An electric circuit for use with a two-terminal direct current source and a two-terminal load where a first load terminal is connected to a first source terminal and where said circuit is connected between the second source terminal and the second load terminal across which a variable direct voltage is developed said electric circuit comprising: a first transistor having emitter, base and collector electrodes; said emitter and collector electrodes being respectively connected to said second source terminal and said second load terminal; biasing means coupled to said base electrode for biasing said first transistor into saturation; a second transistor having emitter, base, and collector electrodes; said second transistor emitter electrode being connected to said first transistor emitter electrode; said second transistor collector electrode being connected to said biasing means; biasing means coupled to said second transistor base electrode for biasing said second transistor to cutoff; said second transistor biasing means coupling a portion of the voltage developed across said second source terminal and second load terminal to said second transistor base electrode whereby at a predetermined level said voltage switches said second transistor into saturation and said first transistor into cutoff, said circuit remaining in this condition until the current flow between said current source and said load is cutoff.

Claim 25

A two-terminal current regulator comprising: a pair of terminals; a first semiconductor device having emitter, base and collector electrodes; means connecting the emitter-to-collector current path of said first device between said pair of terminals; a second semiconductor device having emitter, base and collector electrodes; means including an impedance element connecting the emitter-to-collector current path of said second device between said pair of terminals in a manner that one terminal of said impedance is connected to the collector electrode of said first transistor; means connecting the other terminal of said impedance element to the base electrode of said first transistor; means providing a voltage divider connected between said pair of terminals and across which a variable direct voltage is developed; and means connecting the base electrode of said second transistor to said voltage divider to maintain said second transistor cutoff until the current between said pair of terminals through the emitter-to-collector current path of said first transistor reaches a predetermined magnitude.

Claim 26

A two-terminal current regulator comprising: a pair of terminals; a first semiconductor device having emitter, base and collector electrodes; means connecting the emitter-to-collector current path of said first device between said pair of terminals; a second semiconductor device having emitter, base and collector electrodes; means including an impedance element connecting the emitter-to-collector current path of said second device between said pair of terminals in a manner that one terminal of said impedance is connected to the collector electrode of said first transistor; means connecting the other terminal of said impedance element to the base electrode of said first transistor; means providing a voltage divider connected between said pair of terminals and across which a variable direct voltage is developed; and means connecting the base electrode of said second transistor to said voltage divider to maintain said second transistor cutoff until the current between said pair of terminals through the emitter-to-collector current path of said first transistor reaches a predetermined magnitude.

Claim 27

A two-terminal current regulator comprising: a pair of terminals across which a variable direct voltage is developed; a transistor having emitter, base and collector electrodes; means connecting the emitter-to-collector current path of the transistor between said pair of terminals; biasing means coupled to the base electrode of said transistor for biasing said transistor into saturation; and means operable to couple a portion of the voltage developed between said pair of terminals due to a predetermined current flow between said pair of terminals to said transistor base to render said transistor nonconductive.

Claim 28

A two-terminal current regulator comprising: a pair of terminals across which a variable direct voltage is developed; a transistor having emitter, base and collector electrodes; means connecting the emitter-to-collector current path of the transistor between said pair of terminals; biasing means coupled to the base electrode of said transistor for biasing said transistor into saturation; and means operable to couple a portion of the voltage developed between said pair of terminals due to a predetermined current flow between said pair of terminals to said transistor base to render said transistor nonconductive.

Claim 29

A two-terminal current regulator comprising: first and second terminals, first and second transistors, each having emitter, base and collector electrodes; means connecting said first transistor emitter electrode to said first terminal; a first resistor connecting said first transistor base electrode to said second terminal; a direct connection from said first transistor collector electrode to said second terminal; second and third resistors serially connected across said first and second terminals; a direct connection from said second transistor emitter electrode to said first terminal; means connecting said second transistor base electrode to the junction of said second and third resistors; and a direct connection from said second transistor collector electrode to said first transistor base electrode.

Claim 30

A two-terminal current regulator comprising: first and second terminals, first and second transistors, each having emitter, base and collector electrodes; means connecting said first transistor emitter electrode to said first terminal; a first resistor connecting said first transistor base electrode to said second terminal; a direct connection from said first transistor collector electrode to said second terminal; second and third resistors serially connected across said first and second terminals; a direct connection from said second transistor emitter electrode to said first terminal; means connecting said second transistor base electrode to the junction of said second and third resistors; and a direct connection from said second transistor collector electrode to said first transistor base electrode.

Claim 31

A two-terminal current regulator as defined in claim 15 wherein said first transistor emitter electrode connecting means includes a fourth resistor.

Claim 32

A two-terminal current regulator as defined in claim 15 wherein said second transistor base electrode connecting means includes a diode.

Claim 33

A two-terminal circuit that exhibits a negative current-voltage characteristic region between first and second positive current-voltage characteristic regions, comprising first and second terminals forming an input and output respectively, first, second and third branches connected in parallel between said first and second terminals, said first branch comprising a first transistor having its emitter connected to said first terminal, and means connecting the collector of said first transistor to said second terminal, said second branch comprising a second transistor having its emitter connected to said first terminal, and resistor means connected between the collector of said second transistor and said second terminal, said first and second transistors being of the same conductivity type, said third branch comprising a resistive voltage divider having a tap, means connecting the base of said first transistor to the collector of said second transistor, means connecting the base of said second transistor to said tap whereby said divider provides the sole direct current for said second transistor, a source of voltage, and means applying said voltage between said first and second terminals, whereby the voltage between said first and second terminals is variable, the resistances of said voltage divider being proportioned to hold said second transistor in a cutoff state in a first range of voltage between said first and second terminals whereby only said first transistor is conductive, and to bias said second transistor to a conductive state for voltages in a second range between said terminals above said first range, whereby the collector current flow of said second transistor through said resistor means decreases the base current of said second transistor, and in a portion of said second range increasing voltages between said terminals produce a decrease in the collector current of said first transistor that is greater than the increase in collector current of said second transistor.

Claim 34

A two-terminal circuit that exhibits a negative current-voltage characteristic region between first and second positive current-voltage characteristic regions, comprising first and second terminals forming an input and output respectively, first, second and third branches connected in parallel between said first and second terminals, said first branch comprising a first transistor having its emitter connected to said first terminal, and means connecting the collector of said first transistor to said second terminal, said second branch comprising a second transistor having its emitter connected to said first terminal, and resistor means connected between the collector of said second transistor and said second terminal, said first and second transistors being of the same conductivity type, said third branch comprising a resistive voltage divider having a tap, means connecting the base of said first transistor to the collector of said second transistor, means connecting the base of said second transistor to said tap whereby said divider provides the sole direct current for said second transistor, a source of voltage, and means applying said voltage between said first and second terminals, whereby the voltage between said first and second terminals is variable, the resistances of said voltage divider being proportioned to hold said second transistor in a cutoff state in a first range of voltage between said first and second terminals whereby only said first transistor is conductive, and to bias said second transistor to a conductive state for voltages in a second range between said terminals above said first range, whereby the collector current flow of said second transistor through said resistor means decreases the base current of said second transistor, and in a portion of said second range increasing voltages between said terminals produce a decrease in the collector current of said first transistor that is greater than the increase in collector current of said second transistor.

Claim 35

A circuit that exhibits a negative resistance characteristic between first ans second terminals forming an input and output respectively, comprising first and second transistors of the same conductivity type, means connecting the emitters of said transistors to said first terminal, means connecting the collector of said first transistor directly to said second terminal, means connecting the collector of said second transistor directly to the base of said first transistor, a resistive voltage divider connected between said first and second terminals, said voltage divider having a tap connected to the base of said second transistor, and resistor means connected between the collector and emitter of said first transistor, the resistors of said divider being proportioned to hold said second transistor cutoff for a first range of voltages between the emitter and collector os said first transistor at which said first transistor is conductive, and to bias said second transistor to a conductive state at a second range of voltages between the emitter and collector of said first transistor above said first range, whereby second transistor collector current increases resulting from increases in emitter-collector voltage of said first transistor are less than first transistor collector current decreases in a portion of said second range.

Claim 36

A circuit that exhibits a negative resistance characteristic between first ans second terminals forming an input and output respectively, comprising first and second transistors of the same conductivity type, means connecting the emitters of said transistors to said first terminal, means connecting the collector of said first transistor directly to said second terminal, means connecting the collector of said second transistor directly to the base of said first transistor, a resistive voltage divider connected between said first and second terminals, said voltage divider having a tap connected to the base of said second transistor, and resistor means connected between the collector and emitter of said first transistor, the resistors of said divider being proportioned to hold said second transistor cutoff for a first range of voltages between the emitter and collector os said first transistor at which said first transistor is conductive, and to bias said second transistor to a conductive state at a second range of voltages between the emitter and collector of said first transistor above said first range, whereby second transistor collector current increases resulting from increases in emitter-collector voltage of said first transistor are less than first transistor collector current decreases in a portion of said second range.

Claim 37

A two-port circuit that exhibits a negative resistance characteristic, comprising a source of potential, a first transistor, means connecting said source between the emitter and collector of said first transistor, a second transistor of the same conductivity type as said first transistor having its collector connected directly to the base of said first transistor, means connecting the emitter of said second transistor to the emitter of said first transistor, a resistive voltage divider connected between the emitter and collector of said first transistor, said divider having a tap connected to the base of said second transistor for providing the sole direct current bias for said second transistor, and resistor means connected between the collector and base of said second transistor, said divider being proportioned to hold said second transistor cut off for a first range of emitter-collector voltages of said first transistor during which said first transistor is conductive, and to bias said second transistor to a conductive state for a second range of emitter-collector voltages, of said first transistor above said first range, whereby a negative resistance characteristic occurs between the emitter and collector of said first transistor during a portion of said second range of emitter-collector voltages of said first transistor.

Claim 38

A two-port circuit that exhibits a negative resistance characteristic, comprising a source of potential, a first transistor, means connecting said source between the emitter and collector of said first transistor, a second transistor of the same conductivity type as said first transistor having its collector connected directly to the base of said first transistor, means connecting the emitter of said second transistor to the emitter of said first transistor, a resistive voltage divider connected between the emitter and collector of said first transistor, said divider having a tap connected to the base of said second transistor for providing the sole direct current bias for said second transistor, and resistor means connected between the collector and base of said second transistor, said divider being proportioned to hold said second transistor cut off for a first range of emitter-collector voltages of said first transistor during which said first transistor is conductive, and to bias said second transistor to a conductive state for a second range of emitter-collector voltages, of said first transistor above said first range, whereby a negative resistance characteristic occurs between the emitter and collector of said first transistor during a portion of said second range of emitter-collector voltages of said first transistor.

Claim 39

A circuit that exhibits a negative resistance characteristic comprising first and second terminals forming an input and output respectively, a source of potential, means applying said potential between said first and second terminals, first and second transistors of the same conductivity type, means connecting the emitter of said first transistor to said first terminal, means connecting the emitter of said second transistor to said first terminal, resistor means having one end connected to the collector of said first transistor, means connecting the other end of said resistor means to the base of said first transistor and the collector of said second transistor, whereby the only current flow through said resistor means is the base current of said first transistor and collector current of said second transistor, means connecting the collector of said first transistor to said second terminal, and a resistive voltage divider connected between said first terminal and the collector of said first transistor, said divider having a tap providing the sole direct bias for said second transistor, said divider being proportioned to hold said second transistor cut off for a first range of emitter-collector voltages of said first transistor during which said first transistor is conductive, and to bias said second transistor to a conductive state for a second range of emitter-collector voltages of said first transistor above said first range, whereby a negative resistance characteristic occurs between the emitter and collector of said first transistor during a portion of said second range of emitter-collector voltages of said first transistor.

Claim 40

A circuit that exhibits a negative resistance characteristic comprising first and second terminals forming an input and output respectively, a source of potential, means applying said potential between said first and second terminals, first and second transistors of the same conductivity type, means connecting the emitter of said first transistor to said first terminal, means connecting the emitter of said second transistor to said first terminal, resistor means having one end connected to the collector of said first transistor, means connecting the other end of said resistor means to the base of said first transistor and the collector of said second transistor, whereby the only current flow through said resistor means is the base current of said first transistor and collector current of said second transistor, means connecting the collector of said first transistor to said second terminal, and a resistive voltage divider connected between said first terminal and the collector of said first transistor, said divider having a tap providing the sole direct bias for said second transistor, said divider being proportioned to hold said second transistor cut off for a first range of emitter-collector voltages of said first transistor during which said first transistor is conductive, and to bias said second transistor to a conductive state for a second range of emitter-collector voltages of said first transistor above said first range, whereby a negative resistance characteristic occurs between the emitter and collector of said first transistor during a portion of said second range of emitter-collector voltages of said first transistor.

Claim 41

A bistable circuit comprising a negative resistance circuit having first and second terminals, and a source of voltage and an output impedance serially connected between said first and second terminals, said negative resistance circuit comprising a first transistor, means connecting the emitter of said first transistor to said first terminal, means connecting the collector of said first transistor to said second terminal, a second transistor of the same conductivity type as said first transistor, means connecting the emitter of said second transistor to said first terminal, resistance means connected between the base and collector of said first transistor, means connecting the collector of said second transistor to the base of said first transistor, a resistive voltage divider connected between said first terminal and the collector of said first transistor, and a tap on said divider connected to the base of said second transistor.

Claim 42

A bistable circuit comprising a negative resistance circuit having first and second terminals, and a source of voltage and an output impedance serially connected between said first and second terminals, said negative resistance circuit comprising a first transistor, means connecting the emitter of said first transistor to said first terminal, means connecting the collector of said first transistor to said second terminal, a second transistor of the same conductivity type as said first transistor, means connecting the emitter of said second transistor to said first terminal, resistance means connected between the base and collector of said first transistor, means connecting the collector of said second transistor to the base of said first transistor, a resistive voltage divider connected between said first terminal and the collector of said first transistor, and a tap on said divider connected to the base of said second transistor.