US3624468A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Insulated gate field-effect transistor with opposite-type gate connected region inset in source or drain
Assignee: US Philips Corp
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Filing: 1969-04-23
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Granted: 1971-11-30
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Expires: 1989-04-23
Abstract
Abstract An insulated gate field-effect transistor is described in which an additional region of the opposite type conductivity is inset in the source or drain regions and connected to the gate. The additional junction thereby formed is reverse biased during operation. When inset in the drain, the reverse-biased junction provides additional gate-drain capacitance for a Miller integrator circuit, whereas when inset in the source, the additional junction can act as a safety diode between the gate and source. The low breakdown voltage of the additional junction due to the high-impurity content of the regions increases the protection afforded by the safety diode.
Inventors
- 👤 Frederik Leonard Sangster
- 👤 Rijkent Jan Nienhuis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:27
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/472; H10D44/476; G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184; G11C19/186; G11C27/00; G11C27/04; H10D44/462; H10D89/00; H10D89/60; H10D89/601; H10D99/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
40 words
An insulated gate field-effect transistor as set forth in claim 1 wherein the further surface region and the said source region have impurity contents such that the said P-N junction therebetween has a breakdown voltage of at most 15 volts.
Claim 2
Dependent Claim
54 words
An insulated gate field-effect transistor as set forth in claim 2 wherein an input circuit is coupled between the gate and the source region, and an output circuit is coupled between the source and drain regions, whereby the said P-N junction forms a safety diode connected between the gate electrode and the source region.
Claim 3
Dependent Claim
53 words
An insulated gate field-effect transistor as set forth in claim 3 wherein the body portion containing the source and drain regions is P-type but of relatively high resistivity, the source and drain regions are of N-type but of relatively low resistivity, and the further region is of P-type but of relatively low resistivity.
Claim 4
Dependent Claim
23 words
An insulated gate field-effect transistor as set forth in claim 4 wherein means are provided connecting the body portion to the source region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-29 | 1975-05-31 | 1975-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-29 | 1979-05-31 | 1979-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-29 | 1983-05-31 | 1983-11-30 | $7700.00 | Window Closed / Lapsed |