Register control system and method

Claim 2

A plural station web system wherein marks are cyclically applied in line on a web at successive stations, and wherein scanning of the marks for sensing the registration condition of the web at a given station produces a series of successive scanner pulses in each repeat interval, said system comprising a scanner pulse circuit for receiving said series of scanner pulses including at least three successive scanner pulses in each repeat interval and for responding to a selected pair of said scanner pulses to provide respective output signals, and control pulse transmission means connected to said scanner pulse circuit and responsive to the output signals therefrom produced by said pair of scanner pulses to provide a pair of control pulses whose spacing is a measure of the register condition of the web at the given station.

Claim 3

A system according to claim 1 with said scanner pulse circuit including selector switch means having respective switching positions corresponding to successive scanner pulse positions in the series, said switch means being adjustable to condition said scanner pulse circuit to respond to a selected pair of said scanner pulses pertinent to the registration condition at the given station.

Claim 4

A system according to claim 2 with said selector switch means being operable to condition said scanner pulse circuit to respond to any pulse of said series as representing a pertinent maRk applied to the web in advance of the given station and select any other pulse of said series as representing the mark applied to the web at the given station.

Claim 5

A system according to claim 1 with said scanner pulse circuit comprising reset means for responding to encoder pulses produced by uniform increments of movement of the web and automatically operable to cyclically reset the scanner pulse circuit to an initial condition at intervals related to the speed of movement of the web past the station thereby to enable repeated sampling of the registration condition of the web at said station.

Claim 6

A system according to claim 1 with said scanner pulse circuit comprising scanner pulse responsive means shiftable from an initial condition to a succession of further conditions in response to successive scanner pulses of the series, and reset means for cyclically restoring said pulse responsive means to said initial condition in advance of receipt of each series of said scanner pulses.

Claim 7

A system according to claim 5 with said pulse responsive means comprising a shift register wherein successive stages are actuated in response to successive pulses until all stages have been actuated, each stage remaining in actuated condition until reset to initial condition, and said shift register after receipt of a predetermined number of pulses being nonresponsive to any further pulses received prior to resetting of the shift register to the initial condition.

Claim 8

A system according to claim 6 with said reset means comprising a counter circuit including a counter responsive to encoder pulses produced by uniform increments of movement of the web, said counter circuit being operative when the counter reaches a predetermined count value to reset the shift register to said initial condition and to reset said counter to an initial count, said counter circuit being inherently operable to place said scanner pulse circuit in proper operating condition irrespective of which scanner pulse of the series is first received by the scanner pulse circuit at initial start up of the system.

Claim 9

A mark discriminator system for a web having a series of marks at each successive repeat length therealong including one mark substantially representing a reference position on the web and a second mark whose position relative to the one mark is a function of registration condition of the web at a given station, said system comprising input means for receiving scanner pulses which are responsive to the scanning of the respective marks on the web, a scanner pulse circuit connected to said input means to receive a series of scanner pulses in each repeat interval, said circuit comprising digital logic means assuming successive conditions in response to the successive scanner pulses of the series and selectively adjustable to transmit respective output signals in response to the respective scanner pulses corresponding to said one mark and to said second mark, the output signals thereby providing a measure of the register condition of the web.

Claim 10

A mark discriminator system for a web having a series of marks at each successive repeat length therealong including one mark substantially representing a reference position on the web and a second mark whose position relative to the one mark is a function of registration condition of the web at a given station, said system comprising input means for receiving scanner pulses which are responsive to the scanning of the respective marks on the web, a scanner pulse circuit connected to said input means to receive a series of scanner pulses in each repeat interval, said circuit comprising digital logic means assuming successive conditions in response to the successive scanner pulses of the series and selectively adjustable to transmit respective output signals in response to the respective scanner pulses corresponding to said one mark and to said second mark, the output signals thereby providing a measure of the register condition of the web.

Claim 11

A system in accordance with claim 8 with said digital logic means being resettable to an initial condition and being responsive to successive scanner pulses thereafter received up to a predetermined maximum number of scanner pulses, but being nonresponsive to scanner pulses in excess of said predetermined maximum number until reset to said initial condition.

Claim 12

A system in accordance with claim 9 further comprising a counter circuit for counting encoder pulses produced by uniform increments of movement of the web and operable in response to a first of said output signals to begin a counting cycle and operable upon reaching a predetermined count which predetermined count is reached after a time interval which is greater than the time interval between said output signals, to reset said digital logic means to said initial condition, said counter circuit being inherently operable to place said digital logic means in proper operating condition irrespective of which scAnner pulse of said series is first received by said scanner pulse circuit at initial startup of the system.

Claim 13

In a plural station web system wherein first, second, third and fourth marks are cyclically applied in line on a common channel of a web at respective first, second, third and fourth stations, and wherein scanning of the marks for sensing the registration condition of the web produces first, second, third and fourth scanner pulses in each of successive repeat intervals, the improvement comprising one and only one scanner at said fourth station for scanning only a single line of marks on the web and operable for scanning said first, second, third and fourth marks on said common channel of the web in a repeat length of the web to produce a series of scanner pulses in a repeat interval corresponding to scanning of a repeat length of the web, said series including said first, second, third and fourth scanner pulses, a scanner pulse circuit connected with said scanner to receive said series of scanner pulses therefrom in each repeat interval with the first, second, third and fourth scanner pulses occurring in the same order in each repeat interval, said scanner pulse circuit being responsive to the successive scanner pulses of said series in each repeat interval to assume respective different logical switching conditions with respective first, second, third and fourth logical switching conditions corresponding to respective time intervals for the occurrence of the first, second, third and fourth scanner pulses, respectively, in each repeat interval, and said scanner pulse circuit comprising a pair of four position selection means each for selectively producing an output signal in response to a scanner pulse occurring selectively during said first, second, third and fourth logical switching conditions, said selection means being selectively settable to produce output signals in response to any two of said series of scanner pulses in each repeat interval, and thereby being operable regardless of the order of occurrence of said first, second, third and fourth scanner pulses to generate a pair of output signals in each repeat interval corresponding respectively to the time of occurrence of one of said first, second and third scanner pulses and to the time of occurrence of said fourth scanner pulse, with the time interval between said pair of output signals in each repeat interval thereby representing the status of the register condition at said fourth station in the corresponding repeat length of the web.

Claim 14

In a plural station web system wherein first, second, third and fourth marks are cyclically applied in line on a common channel of a web at respective first, second, third and fourth stations, and wherein scanning of the marks for sensing the registration condition of the web produces first, second, third and fourth scanner pulses in each of successive repeat intervals, the improvement comprising one and only one scanner at said fourth station for scanning only a single line of marks on the web and operable for scanning said first, second, third and fourth marks on said common channel of the web in a repeat length of the web to produce a series of scanner pulses in a repeat interval corresponding to scanning of a repeat length of the web, said series including said first, second, third and fourth scanner pulses, a scanner pulse circuit connected with said scanner to receive said series of scanner pulses therefrom in each repeat interval with the first, second, third and fourth scanner pulses occurring in the same order in each repeat interval, said scanner pulse circuit being responsive to the successive scanner pulses of said series in each repeat interval to assume respective different logical switching conditions with respective first, second, third and fourth logical switching conditions corresponding to respective time intervals for the occurrence of the first, second, third and fourth scanner pulses, respectively, in each repeat interval, and said scanner pulse circuit comprising a pair of four position selection means each for selectively producing an output signal in response to a scanner pulse occurring selectively during said first, second, third and fourth logical switching conditions, said selection means being selectively settable to produce output signals in response to any two of said series of scanner pulses in each repeat interval, and thereby being operable regardless of the order of occurrence of said first, second, third and fourth scanner pulses to generate a pair of output signals in each repeat interval corresponding respectively to the time of occurrence of one of said first, second and third scanner pulses and to the time of occurrence of said fourth scanner pulse, with the time interval between said pair of output signals in each repeat interval thereby representing the status of the register condition at said fourth station in the corresponding repeat length of the web.

Claim 15

In a plural station web system wherein first, second and third marks are cyclically applied in line on a common channel of a web at respective first, second and third stations, and wherein scanning of the marks at a fourth station for sensing the register condition of the web produces at least first, second and third scanner pulses in each of successive repeat intervals, the improvement comprising one and only one scanner at said fourth station for scanning only a single line of marks on the web and operable for scanning said first, second and third marks on said common channel of the web in a repeat length of the web to produce a series of scanner pulses in a repeat interval corresponding to scanning of a repeat length of the web, said series including at least said first, second and third scanner pulses, a scanner pulse circuit connected with said scanner to receive said series of scanner pulses therefrom in each repeat interval with the first, second and third scanner pulses occurring in the same order in each repeat interval, said scanner pulse circuit being responsive to the successive scanner pulses of said series in each repeat interval to assume respective different logical switching conditions with respective first, second and third logical switching conditions corresponding to respective time intervals for the occurrence of the first, second and third scanner pulses, respectively, in each repeat interval, said scanner pulsE circuit comprising a multiple position selection means for selectively producing an output signal in response to a scanner pulse occurring selectively at least during said first, second and third logical switching conditions, said multiple position selection means being selectively settable to produce a first output signal in response to any of said first, second and third scanner pulses in each repeat interval, said scanner pulse circuit comprising further means for producing a second output signal synchronized with a web operation at said fourth station, and said scanner pulse circuit including said multiple position selection means and said further means being operable regardless of the order of said first, second and third scanner pulses to generate first and second output signals in each repeat interval corresponding respectively to the time of occurrence of one of said first, second and third scanner pulses and to the time of occurrence of the web operation at the fourth station, with the time interval between said first and second output signals in each repeat interval thereby representing the status of the register condition at said fourth station in the corresponding repeat length of the web.

Claim 16

In a plural station web system wherein first, second and third marks are cyclically applied in line on a common channel of a web at respective first, second and third stations, and wherein scanning of the marks at a fourth station for sensing the register condition of the web produces at least first, second and third scanner pulses in each of successive repeat intervals, the improvement comprising one and only one scanner at said fourth station for scanning only a single line of marks on the web and operable for scanning said first, second and third marks on said common channel of the web in a repeat length of the web to produce a series of scanner pulses in a repeat interval corresponding to scanning of a repeat length of the web, said series including at least said first, second and third scanner pulses, a scanner pulse circuit connected with said scanner to receive said series of scanner pulses therefrom in each repeat interval with the first, second and third scanner pulses occurring in the same order in each repeat interval, said scanner pulse circuit being responsive to the successive scanner pulses of said series in each repeat interval to assume respective different logical switching conditions with respective first, second and third logical switching conditions corresponding to respective time intervals for the occurrence of the first, second and third scanner pulses, respectively, in each repeat interval, said scanner pulsE circuit comprising a multiple position selection means for selectively producing an output signal in response to a scanner pulse occurring selectively at least during said first, second and third logical switching conditions, said multiple position selection means being selectively settable to produce a first output signal in response to any of said first, second and third scanner pulses in each repeat interval, said scanner pulse circuit comprising further means for producing a second output signal synchronized with a web operation at said fourth station, and said scanner pulse circuit including said multiple position selection means and said further means being operable regardless of the order of said first, second and third scanner pulses to generate first and second output signals in each repeat interval corresponding respectively to the time of occurrence of one of said first, second and third scanner pulses and to the time of occurrence of the web operation at the fourth station, with the time interval between said first and second output signals in each repeat interval thereby representing the status of the register condition at said fourth station in the corresponding repeat length of the web.

Claim 17

In a plural station web system in accordance with claim 12, the improvement further comprising a digital logic circuit resettable to an initial logical switching condition and being responsive to successive scanner pulses thereafter received up to a predetermined maximum number of scanner pulses, but being nonresponsive to scanner pulses in excess of said predetermined maximum number until reset to said initial logical switching condition.

Claim 18

In a plural station web system in accordance with claim 13, the improvement further comprising a counter circuit for counting encoder pulses produced by uniform increments of movement of the web and operable in response to one of said first and second output signals to begin a counting cycle and operable upon reaching a predetermined count which predetermined count is reached after a time interval which is greater than the time interval between said first and second output signals, to reset said digital logic circuit to said initial logical switching condition, said counter circuit being inherently operable to place said digital logic circuit in proper synchronism with said series of scanner pulses irrespective of which scanner pulse of the series is first received at initial start up of the system.