Patent US2374386A successfully refreshed from Google Patents.
Patent US3623073A successfully refreshed from Google Patents.
US3623073A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analogue to digital converters
Assignee: Gemalto Terminals Ltd
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Filing: 1969-05-07
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Granted: 1971-11-23
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Expires: 1989-05-07
Abstract
Abstract In known dual ramp digital voltmeters the ramp up (as the input voltage is integrated) is followed immediately by the ramp down (as the opposing reference voltage is integrated). In this invention there is a small but deliberate delay between ramp up and ramp down which allows conditions to settle and provides an interval during which a reliable polarity determination can be effected.
Inventors
- 👤 Desmond Wheable
- 👤 Stephen H Outram
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:19
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
207 words
A dual ramp analog to digital converter comprising an integrating means, a source of clock pulses, means for counting a first predetermined number of clock pulses to define a first interval, and for counting a second number of clock pulses during a second interval, the second number of pulses providing a digital representation of the analog signal magnitude and the counting means signalling the end of the first interval, means for applying the analog signal to said integrating means during said first interval to cause the output of said integrating circuit to deviate from a datum level, a source of a reference signal means for applying said reference signal to said integrating means in a direction to restore said output to said datum level during said second interval following said firsT interval, means responsive to said integrating means output to detect restoration thereof to said datum level to terminate said second interval, and delay means responsive to said counting means signalling the end of said first interval for disconnecting the analog signal from said integrating means and for timedelaying the application of said reference signal to said integrating means, to provide a delay between the end of said first interval and the beginning of said second interval.
Claim 2
Dependent Claim
207 words
A dual ramp analog to digital converter comprising an integrating means, a source of clock pulses, means for counting a first predetermined number of clock pulses to define a first interval, and for counting a second number of clock pulses during a second interval, the second number of pulses providing a digital representation of the analog signal magnitude and the counting means signalling the end of the first interval, means for applying the analog signal to said integrating means during said first interval to cause the output of said integrating circuit to deviate from a datum level, a source of a reference signal means for applying said reference signal to said integrating means in a direction to restore said output to said datum level during said second interval following said firsT interval, means responsive to said integrating means output to detect restoration thereof to said datum level to terminate said second interval, and delay means responsive to said counting means signalling the end of said first interval for disconnecting the analog signal from said integrating means and for timedelaying the application of said reference signal to said integrating means, to provide a delay between the end of said first interval and the beginning of said second interval.
Claim 3
Dependent Claim
23 words
A dual ramp analog to digital converter according to claim 1, wherein said integrating means is an integrating amplifier with a feedback capacitor.
Claim 4
Dependent Claim
212 words
An analog to digital converter comprising an integrating means, a source of clock pulses, means for counting a first number of clock pulses to signal the end of a first interval, means for applying an analog signal to said integrating means during said first interval to cause the output of said integrating means to deviate from a datum level, sources of first and second reference signals of respective opposite polarities, means for detecting the polarity of said integrating means output, storing means for storing the detected polarity and for correspondingly selecting one of said reference signals, means for applying the selected reference signal to said integrating means to restore said output to datum during a second interval following said first interval, means for causing said counting means to count said clock pulses during said second interval to provide a digital representation of the magnitude of said analog signal, first delay means responsive to said counting means signalling the end of said first interval to render said storing means operative to store the detected polarity a predetermined time after the end of said first interval, and second delay means for delaying the application of said selected reference signal to said integrating means until a predetermined time after said storing means is rendered operative.
Claim 5
Dependent Claim
212 words
An analog to digital converter comprising an integrating means, a source of clock pulses, means for counting a first number of clock pulses to signal the end of a first interval, means for applying an analog signal to said integrating means during said first interval to cause the output of said integrating means to deviate from a datum level, sources of first and second reference signals of respective opposite polarities, means for detecting the polarity of said integrating means output, storing means for storing the detected polarity and for correspondingly selecting one of said reference signals, means for applying the selected reference signal to said integrating means to restore said output to datum during a second interval following said first interval, means for causing said counting means to count said clock pulses during said second interval to provide a digital representation of the magnitude of said analog signal, first delay means responsive to said counting means signalling the end of said first interval to render said storing means operative to store the detected polarity a predetermined time after the end of said first interval, and second delay means for delaying the application of said selected reference signal to said integrating means until a predetermined time after said storing means is rendered operative.
Claim 6
Dependent Claim
22 words
An analog to digital converter according to claim 3, wherein said first interval is defined by a fixed number of clock pulses.
Claim 7
Dependent Claim
39 words
An analog to digit converter according to claim 3, wherein said reference signals are voltages of respective opposite polarities and wherein said means for applying apply the selected reference voltage continuously to said integrating means throughout said second interval.
Claim 8
Dependent Claim
121 words
An analog to digital converter comprising integrating means, a source of clock pulses, counting means for counting said pulses, means for applying an analog input to said integrating means to charge said integrating means to a level determined by an analog input during a first interval, means for terminating said first interval when said counting means assumes a preselected count and for removing the analog input from said integrating means, delay means responsive to said counting means to provide a predetermined delay following said first interval, and means responsive to said delay means to initiate a second interval following said delay and operative in said second interval to discharge said integrating means to provide a digital measure of said analog input.
Claim 9
Dependent Claim
121 words
An analog to digital converter comprising integrating means, a source of clock pulses, counting means for counting said pulses, means for applying an analog input to said integrating means to charge said integrating means to a level determined by an analog input during a first interval, means for terminating said first interval when said counting means assumes a preselected count and for removing the analog input from said integrating means, delay means responsive to said counting means to provide a predetermined delay following said first interval, and means responsive to said delay means to initiate a second interval following said delay and operative in said second interval to discharge said integrating means to provide a digital measure of said analog input.
Claim 10
Independent Claim
147 words
A method of converting an analog signal to a digital signal comprising the steps of applying an analog input signal to the input of a linear integrating device and integrating the analog input signal for a fixed, predetermined first interval of time; disconnecting the input analog signal from the input of the storage device to defer the termination of said first time interval and holding the accumulated signal for a predetermined delay interval at essentially the level reached at said termination of the first interval; applying a reference signal to the storage device to remove the accumulated signal therefrom during a second interval the duration of which is dependent upon the magnitude of the analog input signal; producing clock pulses and counting the pulses produced during said second interval to provide a digital measure thereOf; and determining the polarity of the accumulated signal during the delay interval.
Claim 11
Independent Claim
147 words
A method of converting an analog signal to a digital signal comprising the steps of applying an analog input signal to the input of a linear integrating device and integrating the analog input signal for a fixed, predetermined first interval of time; disconnecting the input analog signal from the input of the storage device to defer the termination of said first time interval and holding the accumulated signal for a predetermined delay interval at essentially the level reached at said termination of the first interval; applying a reference signal to the storage device to remove the accumulated signal therefrom during a second interval the duration of which is dependent upon the magnitude of the analog input signal; producing clock pulses and counting the pulses produced during said second interval to provide a digital measure thereOf; and determining the polarity of the accumulated signal during the delay interval.
Claim 12
Independent Claim
148 words
A method of converting an analog signal magnitude into a digital representation thereof comprising the steps of, applying the analog signal to linear integrating means whereby said means generates a first ramping waveform which departs from a signal level, clocking the time at least from the instant the waveform departs from said level, removing the analog signal from said integrating means after a first predetermined interval of time is clocked, clocking a second time interval of sufficient duration to permit a determination to be made regarding the polarity of said analog signal, and then applying a signal of constant magnitude and of opposite sense to said analog signal to said integrating means whereby a second ramping waveform directed toward said signal level is generated, and clocking the time for said second ramping waveform to attain said signal level to provide a digital representation of the analog signal magnitude.
Claim 13
Independent Claim
148 words
A method of converting an analog signal magnitude into a digital representation thereof comprising the steps of, applying the analog signal to linear integrating means whereby said means generates a first ramping waveform which departs from a signal level, clocking the time at least from the instant the waveform departs from said level, removing the analog signal from said integrating means after a first predetermined interval of time is clocked, clocking a second time interval of sufficient duration to permit a determination to be made regarding the polarity of said analog signal, and then applying a signal of constant magnitude and of opposite sense to said analog signal to said integrating means whereby a second ramping waveform directed toward said signal level is generated, and clocking the time for said second ramping waveform to attain said signal level to provide a digital representation of the analog signal magnitude.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-22 | 1975-05-24 | 1975-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-22 | 1979-05-24 | 1979-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-22 | 1983-05-24 | 1983-11-23 | $7700.00 | Window Closed / Lapsed |