Patent US3622798A successfully refreshed from Google Patents.
US3622798A
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Integrated logic circuit
Assignee: Sony Corp
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Filing: 1969-10-23
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Granted: 1971-11-23
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Expires: 1989-10-23
Abstract
Abstract An integrated circuit having a combinational circuit and two field effect transistors formed on a common semiconductor substrate, and in which the two field effect transistors are made conductive alternately by two clock pulses without a direct current source.
Inventors
- 👤 Shigeyuki Ochi
- 👤 Tetsuo Ando
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:52
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/18; G11C19/182; G11C19/184; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
335 words
An integrated logic circuit for delaying an input signal by one bit period and having only two clock pulse receiving terminals, said integrated circuit comprising a first combinational circuit having an input terminal for receiving an input signal and two output terminals and consisting of at least oNe first field effect transistor, two additional first field effect transistors, a second combinational circuit having an input terminal and two output terminals and consisting of at least one second field effect transistor, two additional second field effect transistors, all of said transistors having a common substrate which is grounded, each of said transistors having a gate electrode, a source electrode and a drain electrode, means connecting in parallel relation the source-drain circuit of each of said first and second field effect transistors with said two output terminals of the respective combinational circuit, means connecting the gate electrode of one of said additional first and second field effect transistors with one of said output terminals of said first and second combinational circuits, respectively, means connecting the source-drain circuit of the other of said additional first and second field effect transistors with the other of the output terminals of said first and second combinational circuits, respectively, means connecting said source-drain circuit of said other additional first field effect transistor with said input terminal of the second combinational circuit, means for supplying a first clock pulse to the gate electrodes of said one additional first field effect transistor and said other additional second field effect transistor by way of one of said two clock pulse receiving terminals, and means for supplying a second clock pulse to the gate electrodes of said other additional first field effect transistor and said one additional second field effect transistor by way of the other of said two clock pulse-receiving terminals, said second clock pulse avoiding overlapping with said first clock pulse, whereby said input signal delayed by one bit period is obtained through the source-drain circuit of said other additional second field effect transistor.
Claim 2
Dependent Claim
335 words
An integrated logic circuit for delaying an input signal by one bit period and having only two clock pulse receiving terminals, said integrated circuit comprising a first combinational circuit having an input terminal for receiving an input signal and two output terminals and consisting of at least oNe first field effect transistor, two additional first field effect transistors, a second combinational circuit having an input terminal and two output terminals and consisting of at least one second field effect transistor, two additional second field effect transistors, all of said transistors having a common substrate which is grounded, each of said transistors having a gate electrode, a source electrode and a drain electrode, means connecting in parallel relation the source-drain circuit of each of said first and second field effect transistors with said two output terminals of the respective combinational circuit, means connecting the gate electrode of one of said additional first and second field effect transistors with one of said output terminals of said first and second combinational circuits, respectively, means connecting the source-drain circuit of the other of said additional first and second field effect transistors with the other of the output terminals of said first and second combinational circuits, respectively, means connecting said source-drain circuit of said other additional first field effect transistor with said input terminal of the second combinational circuit, means for supplying a first clock pulse to the gate electrodes of said one additional first field effect transistor and said other additional second field effect transistor by way of one of said two clock pulse receiving terminals, and means for supplying a second clock pulse to the gate electrodes of said other additional first field effect transistor and said one additional second field effect transistor by way of the other of said two clock pulse-receiving terminals, said second clock pulse avoiding overlapping with said first clock pulse, whereby said input signal delayed by one bit period is obtained through the source-drain circuit of said other additional second field effect transistor.
Claim 3
Dependent Claim
35 words
An integrated logic circuit according to claim 1, in which said first and second clock pulses are timed to render said additional first field effect transistors and said additional second field effect transistors alternately conductive.
Claim 4
Dependent Claim
40 words
An integrated logic circuit according to claim 1, in which a capacitor is connected between said other output terminal of each of said combinational circuits and said gate electrode of said other additional first and second field effect transistors, respectively.
Claim 5
Dependent Claim
25 words
An integrated logic circuit according to claim 1, wherein at least one of said combinational circuits is in the configuration of an AND gate circuit.
Claim 6
Dependent Claim
25 words
An integrated logic circuit according to claim 1, wherein at least one of said combinational circuits is in the configuration of an OR gate circuit.
Claim 7
Dependent Claim
24 words
An integrated logic circuit according to claim 1, wherein at least one of said combinational circuits is in the configuration of a bridge circuit.
References Cited (Backward Citations)
US3524077A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-22 | 1975-05-24 | 1975-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-22 | 1979-05-24 | 1979-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-22 | 1983-05-24 | 1983-11-23 | $7700.00 | Window Closed / Lapsed |