Threshold-responsive regenerative latching circuit

Claim 2

A latching circuit having first and second bistable states and adapted to be connected to two different current paths carrying input currents which are differentially varied in response to an input signal, said latching circuit comprising: a. biasing means electrically independent of said current paths for normally applying a threshold bias to said latching circuit to maintain the latching circuit in said first bistable state, and b. means responsive to a predetermined differential change in said currents for causing said latching circuit to regeneratively switch to said second bistable state, whereby the threshold bias is unaffected by said currents.

Claim 3

A latching circuit as defined in claim 1 further comprising: a. first and second transistors having their emitters connected to a common point, b. a third transistor having its base connected to one of said current paths and to said biasing means and having its emitter connected to the base of said first transistor, c. a fourth transistor having its emitter connected to the base of said second transistor, said first transistor being normally relatively nonconducting and said second transistor being normally relatively conducting, thereby defining said first bistable state, said third and fourth transistors being always relatively conducting, d. first terminal means for applying a negative-bias voltage to said common point and the emitters of said third and fourth transistors, and e. second terminal means for applying a positive-bias voltage to the collectors of said first, second, third and fourth transistors and to the bases of said third and fourth transistors, so that said predetermined differential change in said currents renders said first transistor relatively conducting and said second transistor relatively nonconducting, whereby said latching circuit regeneratively switches to said second bistable state, and said fourth transistor prevents said first transistor from becoming saturated.

Claim 4

A latching circuit as defined in claim 3 further comprising: a. a reset circuit connected to said biasing means for applying a reset signal to said latching circuit, thereby to render said first transistor relatively nonconducting and said second transistor relatively conducting to return said latching circuit to said first bistable state.

Claim 5

A latching circuit as defined in claim 3 wherein said biasing means comprises a pair of matched transistors connected between said first and second terminal means for applying a fixed threshold-bias voltage to the base of said third transistor.