Patent US3621291A successfully refreshed from Google Patents.
US3621291A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nodable field-effect transistor driver and receiver circuit
Assignee: Boeing North American Inc
•
Filing: 1970-09-08
•
Granted: 1971-11-16
•
Expires: 1990-09-08
Abstract
Abstract A field-effect transistor driver circuit using a feedback capacitor at the output stage unconditionally charges an output node at least during a first phase recurring clock signal and the input to the driver is evaluated during a second phase recurring clock signal so that the output is conditionally discharged as a function of the input. One or more drivers may be connected at a common output node for implementing a logic function. A receiver pre-output node is precharged during the driver output precharge phase and the receiver output is precharged unconditionally during the driver evaluation phase. The common output node for the driver circuit is evaluated as an input to the receiver so that the receiver output is conditionally discharged as a function of the voltage at the common output node. After the receiver output has been evaluated, it is isolated until the next clock cycle.
Inventors
- 👤 Ted Y Fujimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
225 words
A nodable multiphase field-effect transistor driver and receiver circuit comprising, an output, at least one field-effect transistor driver connected to said output including a first field-effect transistor for unconditionally setting said output to a first voltage level representing a first logic state during one phase of a multiphase clock cycle, and a second field-effect transistor for conditionally resetting said output to a second voltage level representing a second logic state during a second phase of said multiphase clock cycle as a function of the logic state of an input to said driver, a field-effect transistor receiver circuit including an output and having said first recited output connected as an input to said receiver circuit including, third and fourth field-effect transistors for precharging the receiver output during said second recited phase of said multiphase clock cycle, and a fifth field-effect transistor connected in electrical series with said fourth field-effect transistor between said receiver oUtput and said first recited output, said third field-effect transistor is connected at a common point between said fourth and fifth field-effect transistors, said third field-effect transistor being conductive during said first recited phase for precharging the common point between said fourth and fifth field-effect transistors, said fourth and fifth field-effect transistors being operable during a subsequent phase of said multiphase clock cycle for connecting said receiver output to said first recited output.
Claim 2
Dependent Claim
225 words
A nodable multiphase field-effect transistor driver and receiver circuit comprising, an output, at least one field-effect transistor driver connected to said output including a first field-effect transistor for unconditionally setting said output to a first voltage level representing a first logic state during one phase of a multiphase clock cycle, and a second field-effect transistor for conditionally resetting said output to a second voltage level representing a second logic state during a second phase of said multiphase clock cycle as a function of the logic state of an input to said driver, a field-effect transistor receiver circuit including an output and having said first recited output connected as an input to said receiver circuit including, third and fourth field-effect transistors for precharging the receiver output during said second recited phase of said multiphase clock cycle, and a fifth field-effect transistor connected in electrical series with said fourth field-effect transistor between said receiver oUtput and said first recited output, said third field-effect transistor is connected at a common point between said fourth and fifth field-effect transistors, said third field-effect transistor being conductive during said first recited phase for precharging the common point between said fourth and fifth field-effect transistors, said fourth and fifth field-effect transistors being operable during a subsequent phase of said multiphase clock cycle for connecting said receiver output to said first recited output.
Claim 3
Dependent Claim
32 words
The circuit recited in claim 1 including a plurality of field-effect transistor drivers connected at said output for implementing a logic function at an output node common to all of said drivers.
Claim 4
Dependent Claim
166 words
The circuit recited in claim 1 further including a sixth field-effect transistor connected between the gate electrode of said second field-effect transistor and the driver input, said sixth field-effect transistor being conditionally conductive as a function of the input state for controlling the voltage applied to the gate electrode of said second field-effect transistor at least during said second recited phase, said sixth field-effect transistor including a capacitor connected between one electrode and its gate electrode for feeding back the voltage on said one electrode to said gate electrode at least during said second recited phase for enhancing the conduction of said sixth field-effect transistor whereby the voltage on the gate electrode of said second field-effect transistor is increased, the other electrode of said sixth field-effect transistor being connected to a major-phase clock signal for rendering said sixth field-effect transistor conductive during said second recited phase and during said recited subsequent phase as a function of the logic state of an input signal to said driver.
Claim 5
Dependent Claim
207 words
The circuit recited in claim 3 wherein said multiphase clock cycle comprises four phases, said first recited output being unconditionally charged to a first voltage level at least during the second one of said four phases, said common point between said fourth and fifth field-effect transistors being charged to a voltage level simultaneously during said second phase, said first recited output being reset to said second voltage level as a function of the driver input during the third phase of said four-phase clock cycle, said receiver output being set to said first voltage level during said third phase, said receiver output being connected to said first recited output during the fourth phase of said four-phase clock cycle, said second field-effect transistor being conductive during said fourth phase as a function of the logic state of the input for enabling said receiver output to be reset to said second voltage level as a function of the logic state of said first recited output, the voltage on the gate electrode of said sixth field-effect transistor being unconditionally set to a first voltage level during the first phase of said four-phase clock cycle and conditionally reset to a second voltage level during said second phase of the four-phase clock cycle.
Claim 6
Dependent Claim
109 words
The circuit recited in claim 3 wherein said first field-effect transistor is gated by a first major-phase clock signal, said third field-effect transistor is gated by a second major-phase clock signal having one phase overlapping said first major-phase clock signal, said second and fourth field-effect transistors being gated by a third major-phase clock signal having one phase overlapping said second major-phase clock signal, said second field-effect transistor being gated by said third major-phase clock signal as a function of the logic state of an input to said driver, said fifth field-effect transistor being gated by a fourth major-phase clock signal having one phase overlapping said third major-phase clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-15 | 1975-05-17 | 1975-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-15 | 1979-05-17 | 1979-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-15 | 1983-05-17 | 1983-11-16 | $7700.00 | Window Closed / Lapsed |