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US3621279A
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High-density dynamic shift register
Assignee: International Business Machines Corp
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Filing: 1970-01-28
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Granted: 1971-11-16
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Expires: 1990-01-28
Abstract
Abstract A dynamic shift register is disclosed for providing large capacity storage of digital data information in a small-volume solid-state package. A unique high-density approach is taken, involving a cell comprising n subcells capable of storing n-1 bits of data. The cells are fabricated preferably of field effect transistors embedded in a semiconductor wafer or monolith.
Inventors
- 👤 Teh-Sen Jen
- 👤 Wilbur D Pricer
- 👤 Norbert G Vogl Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:28
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184; G11C19/186; H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
174 words
A shift register for storing digital bits of data comprising: a. at least one group of interconnected gated registers or subcells for storing n-1 bits of data, each of said gated registers or subcells including storage means, and input and output terminal means, b. the total number of gated registers or subcells being less than 2(n-1) , c. less than 2(n-1) control terminals being associated with the less than 2Cn-1) gated registers, d. each of said less than 2(n-1) control terminals being adapted to receive an indivIdual set of clock signals, the total number of distinct sets of clock signals being greater than two for transferring digital information between said gated registers or subcells, and wherein each individual ones of said greater than two sets of clock signals is effective, in conjunction with a digital bit of data being applied to an input terminal means, to store a digital bit of data in its associated gated register and provide an output signal level representative of the digital bit at its respective output terminal means.
Claim 2
Dependent Claim
174 words
A shift register for storing digital bits of data comprising: a. at least one group of interconnected gated registers or subcells for storing n-1 bits of data, each of said gated registers or subcells including storage means, and input and output terminal means, b. the total number of gated registers or subcells being less than 2(n-1) , c. less than 2(n-1) control terminals being associated with the less than 2Cn-1) gated registers, d. each of said less than 2(n-1) control terminals being adapted to receive an indivIdual set of clock signals, the total number of distinct sets of clock signals being greater than two for transferring digital information between said gated registers or subcells, and wherein each individual ones of said greater than two sets of clock signals is effective, in conjunction with a digital bit of data being applied to an input terminal means, to store a digital bit of data in its associated gated register and provide an output signal level representative of the digital bit at its respective output terminal means.
Claim 3
Dependent Claim
60 words
A shift register for storing digital bits of information as in claim 1: a. wherein the total number of gated registers or subcells of said at least one group is n, and b. the number of said control terminal being n, each one of said n control terminals being adapted to receive one of n distinct sets of clock signals.
Claim 4
Dependent Claim
23 words
A shift register as in claim 2 wherein the shift register is comprised of said sole group of interconnected gated registers or subcells.
Claim 5
Dependent Claim
40 words
A shift register as in claim 2 wherein the shift register is comprised of a plurality of groups of interconnected gated registers or subcells, each group being identical to said at least one group of interconnected gated registers or subcells.
Claim 6
Dependent Claim
30 words
A shift register for storing digital bits of information as in claim 2 wherein said gated registers or subcells of said at least one group comprise a semiconductor monolithic structure.
Claim 7
Dependent Claim
30 words
A shift register for storing bits of information as in claim 5 wherein said gated registers or subcells comprise field effect transistors, and said storage means comprise a parasitic capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-15 | 1975-05-17 | 1975-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-15 | 1979-05-17 | 1979-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-15 | 1983-05-17 | 1983-11-16 | $7700.00 | Window Closed / Lapsed |