Patent US3619670A successfully refreshed from Google Patents.
US3619670A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Elimination of high valued {37 p{38 {0 resistors from mos lsi circuits
Assignee: Boeing North American Inc
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Filing: 1969-11-13
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Granted: 1971-11-09
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Expires: 1989-11-13
Abstract
Abstract The circuit of the invention is capable of maintaining a static output, the level of which is at least as great as the circuit''s potential supply. The circuit is comprised of complementary transistorized bootstrap circuits each of which uses a storage capacitor between the output of the transistorized bootstrap circuit and the gate of the output transistor of the bootstrap circuit, to temporarily maintain the output from each bootstrap circuit at the potential supply. Clocking means are provided to overlap the outputs from each bootstrap circuit so as to maintain the component''s output at the level of the potential supply. Gating means are provided for logically switching the output between a reference potential such as ground and the potential supply.
Inventors
- 👤 Gary L Heimbigner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
116 words
A transistorized circuit comprising in combination: a. a source of potential; b. an input terminal and an output terminal; c. a gated two-state load means connected between said source of potential and said output terminal, one of said states being low conductance and the other high conductance; d. a complementary pair of bootstrap means connected to said load means to gate said load means between said two states; e. clocking means, clocking said pair of bootstrap means into overlapping conductance; and f. logic means connected between said output terminal and a reference point, and having its input connected to said input terminal, to switch the output signal between said reference point and said source of potential.
Claim 2
Dependent Claim
116 words
A transistorized circuit comprising in combination: a. a source of potential; b. an input terminal and an output terminal; c. a gated two-state load means connected between said source of potential and said output terminal, one of said states being low conductance and the other high conductance; d. a complementary pair of bootstrap means connected to said load means to gate said load means between said two states; e. clocking means, clocking said pair of bootstrap means into overlapping conductance; and f. logic means connected between said output terminal and a reference point, and having its input connected to said input terminal, to switch the output signal between said reference point and said source of potential.
Claim 3
Dependent Claim
19 words
The invention according to claim 1 wherein said clocking means connects said bootstrapping means to the common reference point.
Claim 4
Dependent Claim
13 words
a storage capacitor connected between the source and gate of said first transistor.
Claim 5
Dependent Claim
13 words
a storage capacitor connected between the source and gate of said first transistor.
Claim 6
Dependent Claim
116 words
a second field effect transistor, the drain and gate of which are connected to said potential source, and the source of which is connected to the gate of said first transistor so as to charge said storage capacitor through a high conductance path and to provide a low conductance discharge path when said storage capacitor is charged; e. clocking means connected to the sources of said first field effect transistors for clocking said pair of bootstrap means into overlapping conductance; and f. logic means connected between said output terminal and the reference point, and having its input connected to said input terminal, to switch the output signal between the reference point and said source of potential.
Claim 7
Dependent Claim
116 words
a second field effect transistor, the drain and gate of which are connected to said potential source, and the source of which is connected to the gate of said first transistor so as to charge said storage capacitor through a high conductance path and to provide a low conductance discharge path when said storage capacitor is charged; e. clocking means connected to the sources of said first field effect transistors for clocking said pair of bootstrap means into overlapping conductance; and f. logic means connected between said output terminal and the reference point, and having its input connected to said input terminal, to switch the output signal between the reference point and said source of potential.
Claim 8
Dependent Claim
125 words
The invention according to claim 1 wherein each of said bootstrapping means is comprised of: a. a first field effect transistor, the drain of which is connected to said potential source, the source of which is connected to said clocking means, and the gate of which is connected to said load means; b. a storage capacitor connected between said source and gate of said first transistor; and c. a second field effect transistor, the drain and gate of which are connected to said potential source, and the source of which is connected to the gate of said first transistor so as to charge said storage capacitor through a high conductance path and to provide a low conductance discharge path when said storage capacitor is charged.
Claim 9
Dependent Claim
69 words
The invention according to claim 1 wherein said gated two-state load means is comprised of a pair of field effect transistors, the drains of which are connected to said potential source, the sources of which are connected to said output terminal and the gate of one being connected to one of said bootstrap means, and the gate of the other being connected to the other of said bootstrap means;
Claim 10
Dependent Claim
90 words
The invention according to claim 3 wherein said clocking means comprises: a. a pair of field effect transistors, one for each of said bootstrapping means, the drains of which are connected to the source of a corresponding first transistor and the sources of which are connected to the common reference point and the gates of which are connected to a source of two-phase clocking so as to alternately turn said pair of field effect transistors on and off at a rate which substantially maintains the charge on said stOrage capacitors.
Claim 11
Dependent Claim
58 words
A transistorized circuit comprising in combination: a. a source of potential; b. an input terminal and an output terminal; c. a pair of load acting field effect transistors, the drains of which are connected to said potential source, and the sources of which are connected to said output terminal; d. a pair of bootstrapping means, each comprised of:
Claim 12
Dependent Claim
58 words
A transistorized circuit comprising in combination: a. a source of potential; b. an input terminal and an output terminal; c. a pair of load acting field effect transistors, the drains of which are connected to said potential source, and the sources of which are connected to said output terminal; d. a pair of bootstrapping means, each comprised of:
Claim 13
Dependent Claim
19 words
The invention according to claim 6 wherein said clocking means connects said bootstrapping means to the common reference point.
Claim 14
Dependent Claim
90 words
The invention according to claim 6 wherein said clocking means comprises: a. a pair of field effect transistors, one for each of said bootstrapping means, the drains of which are connected to the source of a corresponding first transistor and the sources of which are connected to the common reference point and the gates of which are connected to a source of two-phase clocking so as to alternately turn said pair of field effect transistors on and off at a rate which substantially maintains the charge on said storage capacitors.
References Cited (Backward Citations)
US3215861A
Cited
US3417262A
Cited
US3363115A
Cited
US3430071A
Cited
US3393325A
Cited
US3484625A
Cited
US3506851A
Cited
US3524077A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-08 | 1975-05-10 | 1975-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-08 | 1979-05-10 | 1979-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-08 | 1983-05-10 | 1983-11-09 | $7700.00 | Window Closed / Lapsed |