§
Luxuse
Patent Intelligence
Sign In
Patent US3619665A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3619665A Expired / Lapsed US ⏱️ 0.0 years remaining

Optically settable flip-flop

Assignee: RCA Corp
•
Filing: 1969-10-15
•
Granted: 1971-11-09
•
Expires: 1989-10-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An electrically and optically settable flip-flop is disclosed which includes, in integrated circuit form, an MOS flip-flop memory cell including first and second cross-coupled transistors coupled through respective third and fourth load transistors to a source of potential. A photodiode is connected from the cross connection between the output of said first transistor and the input of said second transistor to the substrate, whereby the photodiode is charged substantially to the source potential when the flip-flop is in its reset state with the first transistor cut off and the second transistor conductive. Interruption of the coupling of potential to the first transistor isolates the photodiode. Light energy directed to the photodiode renders it conductive to reduce the voltage at the input of the second transistor until its output turns on the first transistor, whereby the flip-flop is set. Restoring the coupling of bias potential to the first transistor causes the existing electrical state of the flip-flop to be maintained.

Inventors

  • 👤 Walter Frank Kosonocky

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 22:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C7/00; G11C7/20; H; H10; H10D; H10D84/00; H10D84/80; H10D84/811

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 135 words
An electrically and optically settable memory element, comprising a bistable MOS memory cell including first and second crosscoupled transistors coupled through respective third and fourth load impedances to a source of potential, said transistors each having a source, a drain and a gate, the drain of each transistor being cross-coupled to the gate of the other transistor, and a photodiode having one side connected to the drain of said first transistor and to the gate of said second transistor and having the other side returned to a reference potential, said photodiode being thereby reverse biased and charged substantially to said potential when said first transistor is cut off and said second transistor is conductive, and a discharging of said photodiode causes said second transistor to be cut off and said first transistor to be conductive.
Claim 2
Dependent Claim 135 words
An electrically and optically settable memory element, comprising a bistable MOS memory cell including first and second crosscoupled transistors coupled through respective third and fourth load impedances to a source of potential, said transistors each having a source, a drain and a gate, the drain of each transistor being cross-coupled to the gate of the other transistor, and a photodiode having one side connected to the drain of said first transistor and to the gate of said second transistor and having the other side returned to a reference potential, said photodiode being thereby reverse biased and charged substantially to said potential when said first transistor is cut off and said second transistor is conductive, and a discharging of said photodiode causes said second transistor to be cut off and said first transistor to be conductive.
Claim 3
Dependent Claim 48 words
A memory element as defined in claim 1 wherein said transistors include a source and a drain of one conductivity type on a substrate of another conductivity type, and wherein the one side of said photodiode is constituted by an extension of the drain of said first transistor.
Claim 4
Dependent Claim 40 words
A memory element as defined in claim 1 and, in addition, means to interrupt the coupling of said potential to said first transistor and said photodiode, whereby light energy directed to said photodiode causes a setting of said memory cell.
Claim 5
Dependent Claim 35 words
A memory element as defined in claim 3, and in addition, means to restore the coupling of said potential to said first transistor and photodiode to maintain the existing electrical state of the memory cell.
Claim 6
Dependent Claim 82 words
A memory element as defined in claim 1, and in addition, means to interrupt the coupling of said potential to said first transistor and said photodiode, means to direct light energy to said photodiode to render it conductive to reduce the voltage coupled to the input of said second transistor until its output turns on said first transistor, and means to restore the coupling of bias potential to said first transistor and photodiode to maintain the existing electrical state of the flip-flop.

References Cited (Backward Citations)

US3189745A Cited
US3104323A Cited
US3284782A Cited
US3463928A Cited
US3514765A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-11-08 1975-05-10 1975-11-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-11-08 1979-05-10 1979-11-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-11-08 1983-05-10 1983-11-09 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag