US3619657A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power control switch
Assignee: United States Department of the Navy
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Filing: 1969-04-02
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Granted: 1971-11-09
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Expires: 1989-04-02
Abstract
Abstract A switching network inhibiting the flow of current from a power supply to a load until the receipt of an actuating signal at the set terminal of a flip-flop within the switching network. The flow of current continues until the actuating signal is removed, an inhibiting signal is received at the reset terminal of the flip-flop and a predetermined fixed period of time has lapsed after receipt of the inhibiting signal.
Inventors
- 👤 Henry Naubereit
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:58
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/30; H03K17/28; H04; H04B; H04B1/00; H04B1/02; H04B1/04
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
147 words
An electrical switch which consumes no power in the standby mode comprising: a flip-flop formed to receive set and reset signals for providing a first signal; a first resistor connected at one terminal to receive said first signal; a second resistor formed to receive at one terminal a second signal; an NPN transistor with the base electrode connected to the other terminal of said first resistor, the collector electrode connected to the other terminal of said second resistor and the emitter electrode grounded; a time delay circuit including a resistor and capacitor connected in parallel with one terminal connected to said NPN transistor collector electrode; and a PNP transistor with the base electrode connected to the other terminal of said parallel connection of said resistor and said capacitor, the emitter electrode formed to receive said second signal and said collector electrode formed to provide an output signal.
Claim 2
Dependent Claim
147 words
An electrical switch which consumes no power in the standby mode comprising: a flip-flop formed to receive set and reset signals for providing a first signal; a first resistor connected at one terminal to receive said first signal; a second resistor formed to receive at one terminal a second signal; an NPN transistor with the base electrode connected to the other terminal of said first resistor, the collector electrode connected to the other terminal of said second resistor and the emitter electrode grounded; a time delay circuit including a resistor and capacitor connected in parallel with one terminal connected to said NPN transistor collector electrode; and a PNP transistor with the base electrode connected to the other terminal of said parallel connection of said resistor and said capacitor, the emitter electrode formed to receive said second signal and said collector electrode formed to provide an output signal.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-08 | 1975-05-10 | 1975-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-08 | 1979-05-10 | 1979-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-08 | 1983-05-10 | 1983-11-09 | $7700.00 | Window Closed / Lapsed |