Patent US3619651A successfully refreshed from Google Patents.
US3619651A
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Digital frequency discriminator
Assignee: ANDERSON JACOBSON Inc
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Filing: 1969-11-07
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Granted: 1971-11-09
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Expires: 1989-11-07
Abstract
Abstract A digital frequency discriminator providing an output of a first level when the frequency of an input signal is above a known frequency, while providing an output of a second level when the input signal frequency is below the known frequency. The discriminator provides two complementary square waves with frequencies corresponding to the input signal frequencies. The two square waves are supplied to set and reset a flip-flop which is clocked by clock pulses, produced by a timing circuit, which is activated by a ramp voltage generator. The latter controls the timing circuit to provide each clock pulse a fixed period after the start of each input signal cycle, the period being equal to one-half the period of one cycle at the known frequency. Added circuitry may be included to control the digital output to be provided only if the input signal is of not less than a minimum frequency.
Inventors
- 👤 Richard A Aldrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:33
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
151 words
A frequency discriminator comprising: first means for receiving a succession of input signals having frequencies to be discriminated with respect to a known frequency for providing two complementary successions of square wave signals having frequencies corresponding to the frequencies of said input signals; second means responsive to one of said two complementary successions of square wave signals for providing a clock pulse at a preselected duration after the start of each signal in said one succession of square wave signals, said preselected duration being equal to one-half the period of a signal at said known frequency; and third means responsive to said two successions of square wave signals and said clock pulses for providing an output of a first level when the frequency of an input signal is above said known frequency and for providing an output of a second level when the input signal frequency is below said known frequency.
Claim 2
Dependent Claim
151 words
A frequency discriminator comprising: first means for receiving a succession of input signals having frequencies to be discriminated with respect to a known frequency for providing two complementary successions of square wave signals having frequencies corresponding to the frequencies of said input signals; second means responsive to one of said two complementary successions of square wave signals for providing a clock pulse at a preselected duration after the start of each signal in said one succession of square wave signals, said preselected duration being equal to one-half the period of a signal at said known frequency; and third means responsive to said two successions of square wave signals and said clock pulses for providing an output of a first level when the frequency of an input signal is above said known frequency and for providing an output of a second level when the input signal frequency is below said known frequency.
Claim 3
Dependent Claim
94 words
The arrangement as recited in claim 1 wherein said third means comprises a clockable flip-flop which is settable to provide an output of said first level if the level of a one of said two successions of square wave signals is of a first value when a clock pulse is applied to said flip-flop, said flip-flop being resettable to provide an output of a second level if the level of the other of said two successions of square wave signals is of said first value when a clock pulse is applied to said flip-flop.
Claim 4
Dependent Claim
53 words
The arrangement as recited in claim 2 wherein said succession of input signals comprises a succession of sinusoidal signals of frequencies which are either above or below said known frequency and said first means comprise means responsive to said succession of sinusoidal signals for providing said two complementary successions of square wave signals.
Claim 5
Dependent Claim
64 words
The arrangement as recited in claim 1 wherein said second means includes ramp voltage generating means which is activated by the start of each square wave signal in said one succession of square wave signals to provide a ramp voltage having a preselected rate of voltage change, and timing means for providing a clock pulse each time said ramp voltage reaches a preselected level.
Claim 6
Dependent Claim
94 words
The arrangement as recited in claim 4 wherein said third means comprises a clockable flip-flop which is settable to Provide an output of said first level if the level of a one of said two successions of square wave signals is of a first value when a clock pulse is applied to said flip-flop, said flip-flop being resettable to provide an output of a second level if the level of the other of said two successions of square wave signals is of said first value when a clock pulse is applied to said flip-flop.
Claim 7
Dependent Claim
53 words
The arrangement as recited in claim 5 wherein said succession of input signals comprises a succession of sinusoidal signals of frequencies which are either above or below said known frequency and said first means comprise means responsive to said succession of sinusoidal signals for providing said two complementary successions of square wave signals.
Claim 8
Dependent Claim
80 words
The arrangement as recited in claim 1 further including an output unit responsive to the levels of the output of said third means, and input signals detecting means coupled to said first means for enabling said output unit to provide an output of either a first level or a second level as a function of the output levels of said third means only if a selected number of input signals are detected by said detecting means during a selected interval.
Claim 9
Dependent Claim
64 words
The arrangement as recited in claim 7 wherein said second means includes ramp voltage generating means which is activated by the start of each square wave signal in said one succession of square wave signals to provide a ramp voltage having a preselected rate of voltage change, and timing means for providing a clock pulse each time said ramp voltage reaches a preselected level.
Claim 10
Dependent Claim
53 words
The arrangement as recited in claim 8 wherein said succession of input signals comprises a succession of sinusoidal signals of frequencies which are either above or below said known frequency and said first means comprise means responsive to said succession of sinusoidal signals for providing said two complementary successions of square wave signals.
Claim 11
Dependent Claim
94 words
The arrangement as recited in claim 9 wherein said third means comprises a clockable flip-flop which is settable to provide an output of said first level if the level of a one of said two successions of square wave signals is of a first value when a clock pulse is applied to said flip-flop, said flip-flop being resettable to provide an output of a second level if the level of the other of said two successions of square wave signals is of said first value when a clock pulse is applied to said flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-08 | 1975-05-10 | 1975-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-08 | 1979-05-10 | 1979-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-08 | 1983-05-10 | 1983-11-09 | $7700.00 | Window Closed / Lapsed |