Patent US3618052A successfully refreshed from Google Patents.
US3618052A
Expired / Lapsed
US
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Bistable memory with predetermined turn-on state
Assignee: Cogar Corp
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Filing: 1969-12-05
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Granted: 1971-11-02
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Expires: 1989-12-05
Abstract
Abstract This disclosure relates to a semiconductor memory arrangement wherein data is preset in a memory array so that there is no need for a supplementary memory, such as a read-only memory, to store the data to be preset. Each memory cell of the semiconductor memory array is predisposed to assume a specific information state upon each application of power thereto. By biasing memory cells in this manner, the desired information is available either upon initial operation or upon the restoration of power subsequent to any power lapse or upon a desired program reset. Hence, a semiconductor memory array is provided which is operable as a Read-Only memory and yet can also function as a Read/Write memory. By writing information into the cells of the array regardless of the initial information state thereof, a Read/Write memory operation is superimposed onto a functioning Read-Only memory.
Inventors
- 👤 Thomas Kwei
- 👤 Robert M Meade
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C17/00; G11C17/08; G11C7/00; G11C7/20; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/2865
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
85 words
A read-write semiconductor memory array comprising, in combination, a plurality of read-write semiconductor memory cells, each of said cells having a ''''one'''' state and a ''''zero'''' state; means for selectively coupling and initially presetting one of said ''''one'''' and ''''zero'''' states into each of said read-write cells, each of said cells of said array having said preset state upon each restoration of electrical energy to the semiconductor memory array; and writing means for superimposing on and changing said preset state in each of said cells.
Claim 2
Dependent Claim
85 words
A read-write semiconductor memory array comprising, in combination, a plurality of read-write semiconductor memory cells, each of said cells having a ''''one'''' state and a ''''zero'''' state; means for selectively coupling and initially presetting one of said ''''one'''' and ''''zero'''' states into each of said read-write cells, each of said cells of said array having said preset state upon each restoration of electrical energy to the semiconductor memory array; and writing means for superimposing on and changing said preset state in each of said cells.
Claim 3
Dependent Claim
42 words
A read-write semiconductor memory array in accordance with claim 1 wherein said selectively coupling and initially presetting means comprises a preset signal line electrically connected to a selected portion of each memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 4
Dependent Claim
42 words
A read-write semiconductor memory array in accordance with claim 1 wherein said selectively coupling and initially presetting means comprises a preset signal line electrically connected to a selected portion of each memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 5
Dependent Claim
41 words
A read-write semiconductor memory array in accordance with claim 1 wherein said selectively coupling and initially presetting means comprises a power line electrically connected to a selected portion of each memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 6
Dependent Claim
69 words
A read-write semiconductor memory array, comprising, in combination, a plurality of read-write semiconductor memory cells having a ''''one'''' state and a ''''zero'''' state; means for selectively coupling and initially presetting one of said ''''one'''' and ''''zero'''' states into each of said cells; means for writing information into said memory cells of said memory array; and means for reading information from said memory cells of said memory array having information.
Claim 7
Dependent Claim
69 words
A read-write semiconductor memory array, comprising, in combination, a plurality of read-write semiconductor memory cells having a ''''one'''' state and a ''''zero'''' state; means for selectively coupling and initially presetting one of said ''''one'''' and ''''zero'''' states into each of said cells; means for writing information into said memory cells of said memory array; and means for reading information from said memory cells of said memory array having information.
Claim 8
Dependent Claim
19 words
A reaD-write semiconductor memory array in accordance with claim 5 wherein each of said cells comprise cross-coupled semiconductor devices.
Claim 9
Dependent Claim
20 words
A read-write semiconductor memory array in accordance with claim 6 wherein each of said semiconductor devices is a bipolar device.
Claim 10
Dependent Claim
42 words
A read-write semiconductor memory array in accordance with claim 5 wherein said selectively coupling and initially presetting means comprises a preset signal line electrically connected to a selected portion of each memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 11
Dependent Claim
39 words
A read-write semiconductor memory array in accordance with claim 8 wherein each of said cells comprises cross-coupled multiemitter devices, said preset signal line is electrically connected to a selected one of said cross-coupled multiemitter devices of each memory cell.
Claim 12
Dependent Claim
46 words
A read-write semiconductor memory array in accordance with claim 9 wherein each of said cross-coupled multiemitter devices comprises a triple emitter transistor type device, said preset signal line is electrically connected to one emitter of said triple emitter transistor type device of one said cross-coupled device.
Claim 13
Dependent Claim
42 words
A read-write semiconductor memory array in accordance with claim 5 wherein said selectively coupling and initially presetting means comprises a pair of bit lines electrically connected to related portions of each memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 14
Dependent Claim
75 words
A read-write semiconductor memory array in accordance with claim 11 wherein each of said cells comprise cross-coupled multiemitter devices, one of said pair of bit lines is electrically connected to one of said cross-coupled multiemitter devices defining one of said ''''one'''' and ''''zero'''' memory states, the other of said pair of bit lines is electrically connected to the other of said cross-coupled multiemitter devices defining the same one of said ''''one'''' or ''''zero'''' memory state.
Claim 15
Dependent Claim
42 words
A read-write semiconductor memory array in accordance with claim 12 wherein each of cross-coupled multiemitter devices comprises a double emitter transistor type device, each of said pair of bit lines being electrically connected to one emitter of each of said cross-coupled devices.
Claim 16
Dependent Claim
40 words
A read-write semiconductor memory array in accordance with claim 5 wherein said selectively coupling and initially presetting means comprises a powerline electrically connected to a selected portion of each memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 17
Dependent Claim
41 words
A read-write semiconductor memory array in accordance with claim 14 wherein each of said cells comprises cross-coupled multiemitter devices, said power line is electrically connected to a resistor of each memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 18
Dependent Claim
27 words
A read-write semiconductor memory array in accordance with claim 15 wherein said resistor is electrically connected to the common collector of one of said cross-coupled multiemitter devices.
Claim 19
Dependent Claim
37 words
A read-write semiconductor memory array in accordance with claim 16 wherein said power line is electrically connected as an intermediate tap to said resistor, each of said cross-coupled multiemitter devices comprises a double emitter transistor type device.
Claim 20
Dependent Claim
69 words
A read-write semiconductor memory cell comprising, in combination, a read-write semiconductor memory cell having a ''''one'''' state and a ''''zero'''' state; means for selectively coupling and initially presetting one of said ''''one'''' and ''''zero'''' states in said cell; said cell having said preset state upon each restoration of electrical energy to the semiconductor memory cell; and writing means for superimposing on and changing said preset state in said cell.
Claim 21
Dependent Claim
69 words
A read-write semiconductor memory cell comprising, in combination, a read-write semiconductor memory cell having a ''''one'''' state and a ''''zero'''' state; means for selectively coupling and initially presetting one of said ''''one'''' and ''''zero'''' states in said cell; said cell having said preset state upon each restoration of electrical energy to the semiconductor memory cell; and writing means for superimposing on and changing said preset state in said cell.
Claim 22
Dependent Claim
42 words
A read-write semiconductor memory cell in accordance with claim 18 wherein said selectively coupling and initially presetting means comprises a preset signal line electrically connected to a selected portion of saId memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 23
Dependent Claim
42 words
A read-write semiconductor memory cell in accordance with claim 18 wherein said selectively coupling and initially presetting means comprises a pair of bit lines electrically connected to related portions of said memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 24
Dependent Claim
41 words
A read-write semiconductor memory cell in accordance with claim 18 wherein said selectively coupling and initially presetting means comprises a power line electrically connected to a selected portion of said memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 25
Dependent Claim
61 words
A read-write semiconductor memory cell comprising, in combination, a read-write semiconductor memory cell having a ''''one'''' state and a ''''zero'''' state; means for selectively coupling and initially presetting one of said ''''one'''' and ''''zero'''' states in said cell; means for writing information into said memory cell; and means for reading information from said memory cell of said memory array having information.
Claim 26
Dependent Claim
61 words
A read-write semiconductor memory cell comprising, in combination, a read-write semiconductor memory cell having a ''''one'''' state and a ''''zero'''' state; means for selectively coupling and initially presetting one of said ''''one'''' and ''''zero'''' states in said cell; means for writing information into said memory cell; and means for reading information from said memory cell of said memory array having information.
Claim 27
Dependent Claim
17 words
A read-write semiconductor memory cell in accordance with claim 22 wherein said cell comprises cross-coupled semiconductor devices.
Claim 28
Dependent Claim
21 words
A read-write semiconductor memory cell in accordance with claim 23 wherein each of said cross-coupled semiconductor devices is a bipolar device.
Claim 29
Dependent Claim
73 words
A read-write semiconductor memory cell in accordance with claim 23 wherein said cell comprises cross-coupled multiemitter devices, one of a pair of bit lines is electrically connected to one of said cross-coupled multiemitter devices defining one of said ''''one'''' and ''''zero'''' memory states, the other of said pair of bit lines is electrically connected to the other of said cross-coupled multiemitter devices defining the same one of said ''''one'''' or ''''zero'''' memory state.
Claim 30
Dependent Claim
43 words
A read-write semiconductor memory cell in accordance with claim 25 wherein each of said cross-coupled multiemitter devices comprises a double emitter transistor type device, each of said pair of bit lines being electrically connected to one emitter of each of said cross-coupled devices.
Claim 31
Dependent Claim
33 words
A read-write semiconductor memory cell in accordance with claim 23 wherein said cell comprises cross-coupled multiemitter devices, a preset signal line is electrically connected to a selected one of said cross-coupled multiemitter devices.
Claim 32
Dependent Claim
46 words
A read-write semiconductor memory cell in accordance with claim 27 wherein each of said cross-coupled multiemitter devices comprises a triple emitter transistor type device, said preset signal line is electrically connected to one emitter of said triple emitter transistor type device of one said cross-coupled devices.
Claim 33
Dependent Claim
38 words
A read-write semiconductor memory cell in accordance with claim 23 wherein said cell comprises cross-coupled multiemitter devices, a powerline is electrically connected to a resistor of each memory cell defining one of said ''''one'''' and ''''zero'''' memory states.
Claim 34
Dependent Claim
27 words
A read-write semiconductor memory array in accordance with claim 29 wherein said resistor is electrically connected to the common collector of one of said cross-coupled multiemitter devices.
Claim 35
Dependent Claim
35 words
A read-write semiconductor memory cell in accordance with claim 30 wherein said power line is electrically connected as an intermediate tap to said resistor, said cross-coupled multiemitter devices comprises a double emitter transistor type device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-01 | 1975-05-03 | 1975-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-01 | 1979-05-03 | 1979-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-01 | 1983-05-03 | 1983-11-02 | $7700.00 | Window Closed / Lapsed |