Patent US3617826A successfully refreshed from Google Patents.
US3617826A
Expired / Lapsed
US
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An integrated transistor with a polycrystalline contact to a buried collector region
Assignee: Sony Corp
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Filing: 1968-11-12
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Granted: 1971-11-02
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Expires: 1988-11-12
Abstract
Abstract Semiconductor devices of the integrated circuit type including contiguous semiconductor regions, portions of these regions containing both a polycrystalline area and a single crystal area.
Inventors
- 👤 Isamu Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:29
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10D62/00; H10D62/40; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/403; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/049; Y10S148/085; Y10S148/098; Y10S148/122; Y10S148/151; Y10S438/00; Y10S438/969
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
248 words
An integrated circuit chip comprising a plurality of layers including a substrate layer of semiconductor material and at least one superimposed layer of semiconductor material above said substrate layer, the uppermost of said layers having monocrystalline regions and polycrystalline regions, said uppermost layer having at least one junction transistor formed in one of said monocrystalline regions, said transistor including an emitter of one conductivity type, a base below said emitter of opposite conductivity type and forming a base-emitter junction therewith and collector below said base of said one conductivity type and forming a collector-base junction therewith, a region of high impurity concentration of the same conductivity type as said collector in the layer immediately below said uppermost layer, which region of high impurity concentration abuts said collector region, said collector region adjacent said base-collector junction having substantially less impurity concentration than said region of high impurity concentration and at least one of said polycrystalline regions being doped with impurities of the same type as said region of high impurity concentration and being of low resistivity from the outer surface of said uppermost layer to said layer therebelow, said low resistivity polycrystalline region being disposed laterally of said transistors and extending through said uppermost layer from the surface of said uppermost layer to a point in contact with said regions of high impurity concentration, whereby there is only a relatively small amount of out-diffusion from said region of high impurity concentration to said collector region adjacent said base-collector junction.
Claim 2
Dependent Claim
289 words
An integrated circuit chip comprising a plurality of layers including a substrate laYer of semiconductor material and at least one superimposed layer of semiconductor material above said substrate layer, the uppermost of said layers having monocrystalline regions and polycrystalline regions, there being regions of seeding site material between said polycrystalline regions and said layer immediately below said uppermost layer, said uppermost layer having at least one junction transistor formed in one of said monocrystalline regions, said transistor including an emitter of one conductivity type, a base below said emitter of opposite conductivity type and forming a base-emitter junction therewith and a collector below said base of said one conductivity type and forming a collector base junction therewith, a region of high impurity concentration of the same conductivity type as said collector in the layer immediately below said uppermost layer, which region of high impurity concentration abuts said collector region, said collector region adjacent said base-collector junction having substantially less impurity concentration than said region of high impurity concentration and at least one of said polycrystalline regions being doped with impurities of the same type as said region of high impurity concentration and being of low resistivity from the outer surface of said uppermost layer to said layer therebelow, said low resistivity polycrystalline region being disposed laterally of said transistors and extending through said uppermost layer from the surface of said uppermost layer to a point in contact with said regions of high impurity concentration, whereby a transistor is provided which has both a low resistance from the surface of said chip through said low resistivity polycrystalline region and said high impurity concentration region to said collector of low impurity concentration and a high breakdown voltage in said base-collector junction.
Claim 3
Dependent Claim
18 words
An integrated circuit chip according to claim 3 in which said seeding site material is vapor deposited silicon.
Claim 4
Dependent Claim
19 words
An integrated circuit chip according to claim 3 in which said seeding site material is an oxide of silicon.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-01 | 1975-05-03 | 1975-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-01 | 1979-05-03 | 1979-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-01 | 1983-05-03 | 1983-11-02 | $7700.00 | Window Closed / Lapsed |