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Method of fabricating a semiconductor integrated circuit device

Assignee: Hitachi Ltd
•
Filing: 1969-07-16
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Granted: 1971-10-26
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Expires: 1989-07-16
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Abstract

Abstract A method of fabricating a semiconductor integrated circuit device in which a plurality of kinds of impurities for defining a collector wall region, a base region and an emitter region are simultaneously diffused by one heat treatment into an epitaxial layer formed on one surface of a semiconductor body with at least one region having a conductivity type opposite to that of the semiconductor body formed in the said one surface, the last named region becoming a part of a collector region, thereby largely reducing the rediffusion of an impurity in the last named region back into the base region to facilitate the control of the base width.

Inventors

  • 👤 Tsugio Makimoto
  • 👤 Michiyoshi Maki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 19:16
CPC Classifications
H; H10; H10P; H10P95/00; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/662; H10P14/668; H10P14/6681; H10P14/6682; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/6923; H10P14/694; H10P14/6943; H10P14/69433; H10W; H10W74/00; H10W74/40; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/043; Y10S148/085; Y10S148/142; Y10S148/151

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 35 words
A method of fabricating a semiconductor integrated circuit device according to claim 1, in which said frame shaped oxide film and oxide mask are formed by chemical vapor deposition of silicon compounds at low temperatures.
Claim 2
Dependent Claim 37 words
A method of fabricating a semiconductor integrated circuit device according to claim 1, in which said semiconductor body consists of a silicon monocrystal having N-type conductivity, said second impurity is phosphorus, and said third impurity is arsenic.
Claim 3
Dependent Claim 63 words
A method of fabricating a semiconductor integrated circuit device according to claim 1, in which said heat treatment is carried out while supplying a fourth impurity determining said second conductivity type together with said third impurity, said fourth impurity being capable of penetrating through said oxide mask into said epitaxial layer thereby reducing the resistivity of the surface portion of said base region.
Claim 4
Dependent Claim 96 words
A method of fabricating a semiconductor integrated circuit device according to claim 4, further comprising the step of forming a second mask on said surface of said epitaxial layer prior to said step of heating said structure, said second mask being of such a material that prevents said fourth impurity from penetrating therethrough and having an aperture located within said opening of said frame shaped oxide layer, said aperture of said first mask being positioned within said aperture of said second mask, thereby diffusing said fourth impurity into a limited surface portion of said base region.
Claim 5
Dependent Claim 50 words
A method of fabricating a semiconductor integrated circuit device according to claim 5, in which said semiconductor body consists of a silicon monocrystal having N-type conductivity, said second impurity is phosphorus, said third impurity is arsenic, said second mask is formed of silicon nitride, and said fourth impurity is gallium.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-10-25 1975-04-26 1975-10-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-10-25 1979-04-26 1979-10-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-10-25 1983-04-26 1983-10-26 $7700.00 Window Closed / Lapsed

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