Process of producing an array of integrated circuits on semiconductor substrate

Claim 2

The process of claim 1 in which the combination of masks is selected by: a. taking a mask from a first one of the levels, b. thereafter comparing the defect-free locations in masks from a second one of the levels with the defect-free locations in the mask from the first one of the levels, c. then selecting a mask from the second level on the basis of the number of the defect-free array locations and the weight of the integrated circuits in the regions in which the defect-free parts are located to maximize the number of defect-free parts of integrated circuits that can be produced with the combination of first and second level masks, d. thereafter comparing the defect-free locations in masks from a third one of the levels with the defect-free locations in the selected combination of first and second level masks, and e. then selecting a mask from the third level on the basis of the number of the defect-free array locations and the weight of the integrated circuits in the regions in which the defect-free parts are located to maximize the number of defect-free parts of integrated circuits that can be produced with the combination of first, second and third level masks.

Claim 3

The process of claim 1 wherein the light-responsive pattern defining medium is photoresist.

Claim 4

A process for preparing an array of monolithic integrated circuits on a semiconductor wafer, using a plurality of masks in successive processing steps to define parts of the integrated circuits, the integrated circuits being subject to randomly occurring defects caused by random defects in the masks, comprising: a. fabricating a number of masks for each processing step, b. inspecting each mask to determine which random positions in the array contain defects in the masks, c. recording the random defects for each mask on a suitable recording medium, d. determining at least two regions of approximately equal but different integrated circuit process yield in the array, e. assigning weights to the integrated circuits in the array based on the determined process yield, f. comparing the location of the defect-free areas in masks for the plurality of processing steps, g. selecting a particular combinaTion of masks for the plurality of processing steps in accordance with the number of the defect-free integrated circuit areas on the masks and the weight of the integrated circuits in the regions in which the defect-free parts are located to maximize the number of nondefective integrated circuits produced in the array, h. coating the semiconductor wafer with a photoresist, i. using a first mask from the selected combination to expose the photoresist, j. carrying out the remainder of a first processing step on the semiconductor wafer, k. coating the semiconductor wafer with photoresist a second time, l. using a second mask from the selected combination to expose the photoresist, m. carrying out the remainder of a second processing step on the semiconductor wafer, and n. continuing the plurality of processing steps on the semiconductor wafer using the remaining masks from the selected combination to expose photoresist on the semiconductor wafer.

Claim 5

The process of claim 3 wherein the light-responsive pattern defining medium is photoresist.