Memory addressing device using arbitrary directed graph structure

Claim 2

A data-processing system comprising a device for addressing with the aid of a computer instruction having an address portion arrayed in accordance with a directed graph structure in the computer store, said store divided into tables, each of said tables having a reference address as a table base and words to be found in numerical sequence relative to the table base in a table are representative of reference addresses for a further table, or operands, or indirect addresses for operands, said addressing device comprising a register for storing an instruction, a register for storing a table word selected from a storage table, and an adder for combining a reference address and a word number resulting in the formation of an absolute table word address for selecting a desired table word, said arrayed address portion of an instruction comprising an arbitrary number of address components for addressing in any directed graph structure, wherein every next-following address component is the number of a word in a table previously located with the aid of a preceding address component or components, said register further including means for selecting the relevant address component for correctly combining an address component with a previously found reference address as a table base in said adder, said means for selecting comprising at least one additional register and a control device for producing a shift of an address component equal to the length thereof in bits, said address component to be processed being available for said adder after said selection in said means for selecting.

Claim 3

A data-processing system as claimed in claim 1 wherein the addressing device comprises a storage element which indicates that there is an instruction having a number of address components or that there is a sequential word having one or more address components continuing the instruction or a preceding sequential word for being processes, said sequential word or words together with the instruction defining a complete operand address, the instructions and any sequential words having, in a field designated for this purpose, a bit indication for the presence or absence of one or, if subsequent ones, one further sequential word by which an instruction counter can be stepped by

Claim 4

A data-processing system as claimed in claim 1 wherein for addressing in said directed graph structure by instructions and sequential words, if any, both having address components of different lengths, the bit lengths of the address components of an instruction and any sequential words being indicated separately in a field of the instruction and in a field of any sequential words, the control device governed from said length field of an instruction and any sequential words produces a variable shift equal to the variable bit length of the address components of the instruction and Any sequential words.

Claim 5

A data-processing system as claimed in claim 3 wherein the bit lengths of the address components of an instruction and any sequential words are indicated in a separate table which is accessible from the length field of the address components of an instruction and any sequential words, said control device being adjustable from said table.

Claim 6

A data-processing system as claimed in claim 1, wherein a table word (T) has a table length field (L) for a next table, and the addressing device comprises a second storage element (FF2), and in that a second adder (AD2) is followed by a sign detector (TD), indicating whether the difference between an address component (a1) and the table length datum (Li) of the table (Ti) concerned defined during an addressing phase in the second adder (AD2) is positive or negative and controlling the second storage element (FF2); if an address component (ai) lies within the table length (Li), the second storage element (FF2) controls a first gate (P1), through which the table reference address (Ti) can be transferred from the register for storing the table word (MR) to the first adder (AD1) and through which first gate (P1) the result of the addition of the address component (ai) to the table reference address (Ti) can be transferred to the selection register (SEL); if an address component (ai) lies beyond the table length (Li), the second storage element (FF2) controls a second gate (P2) and a third gate (P3), the second gate (P2) transferring the table reference address (Ti) as a basic address or, as the case may be, completed to an address in the table where a reference address (T''i) is present as the table base of an overflow table, to the selection register (SEL), where the reference address towards the overflow table base (T''i) is selected, whilst the third gate (P3) is capable of transferring the difference (ai- Li) formed in the second adder (AD2) between the address component (ai) and the table length (Li) towards the register portion (SR) of the selecting the address component, after which in the first adder (AD1) the address (T''i+(ai-Li)) is formed in the overflow table (T''i).

Claim 7

A data-processing system as claimed in claim 5, wherein a table word (T) contains a table class datum (K) of a next table, whilst if the table class datum (K) indicates that an operand table (OT) is following, the addressing precess is interrupted.

Claim 8

A data-processing system as claimed in claim 6 wherein the table class datum (K) contains information about the permission or nonpermission of a further addressing or operation step.