Shift register employing two-phase coupling and transient storage between stages

Claim 2

A serial digital storage arrangement comprising a plurality of cascaded stages wherein a stage comprises: a bistable storage element; and a coupling element; said coupling element including in series: a fast recovery first diode having at least two electrodes, one of which electrodes is coupled to a output node of the bistable storage element; a transistor coupled to the other electrode of the first diode; and a second diode having at least two electrodes, one of which is coupled to the transistor and the other of which is coupled to an output node of the bistable storage element of the next succeeding stage.

Claim 3

A serial digital storage arrangement comprising a plurality of cascaded stage wherein each stage comprises: a bistable storage element having an input node and an output node; and coupling means including a series circuits comprising: a fast recovery diode having at least two electrodes, one of which is coupled to the output node of the bistable storage element; storage means which are not bistable for temporarily storing a signal representative of the digital state of the bistable storage element, said storage means being coupled to the other electrode of the fast recovery diode; and a second diode coupled between the storage means and the input node of the bistable storage elements of the next succeeding stage; means forming a conduction path coupled to the bistable storage element of each stage; and means for switching the potential on said conduction path to the first level for forcing the storage arrangement into a holding mode during which the fast recovery diodes are turned on and the second diodes are turned off and during which in each stage a digital stage is stored in duplicate in the bistable storage element and the temporary storage means of that Stage, and for switching the potential on said conduction path to a second level for forcing the storage arrangement into a shifting mode during which the fast recovery diodes are turned off and the second diodes are turned on and during which information is transferred through the second diodes from the temporary storage means of each stage to the bistable storage element of the next succeeding stage; the apparatus being arranged so that in each stage the time constants of the circuitry attached to said one electrode of the fast recovery diode are smaller than the time constant of the storage means so that when the potential on said conduction path is switched from the second level to the first level for causing the storage arrangement to switch into the shifting mode from the holding mode, the fast recovery diode is switched to a reverse-biased state before the stored digital state is conducted through the second diode to the next succeeding stage.

Claim 4

A serial digital storage arrangement comprising a plurality of cascaded stage wherein each stage comprises: a bistable storage element having an input node and an output node; and coupling means including a series circuits comprising: a fast recovery diode having at least two electrodes, one of which is coupled to the output node of the bistable storage element; storage means which are not bistable for temporarily storing a signal representative of the digital state of the bistable storage element, said storage means being coupled to the other electrode of the fast recovery diode; and a second diode coupled between the storage means and the input node of the bistable storage elements of the next succeeding stage; means forming a conduction path coupled to the bistable storage element of each stage; and means for switching the potential on said conduction path to the first level for forcing the storage arrangement into a holding mode during which the fast recovery diodes are turned on and the second diodes are turned off and during which in each stage a digital stage is stored in duplicate in the bistable storage element and the temporary storage means of that Stage, and for switching the potential on said conduction path to a second level for forcing the storage arrangement into a shifting mode during which the fast recovery diodes are turned off and the second diodes are turned on and during which information is transferred through the second diodes from the temporary storage means of each stage to the bistable storage element of the next succeeding stage; the apparatus being arranged so that in each stage the time constants of the circuitry attached to said one electrode of the fast recovery diode are smaller than the time constant of the storage means so that when the potential on said conduction path is switched from the second level to the first level for causing the storage arrangement to switch into the shifting mode from the holding mode, the fast recovery diode is switched to a reverse-biased state before the stored digital state is conducted through the second diode to the next succeeding stage.

Claim 5

Apparatus as recited in claim 2 wherein the temporary storage means is a transistor.

Claim 6

Apparatus as recited in claim 3 wherein the base electrode of the transistor is coupled to said other electrode of the fast recovery diode and the emitter electrode of the transistor is coupled to the second diode.

Claim 7

Apparatus as recited in claim 2 wherein the fast recovery diode is a Schottky-barrier diode.

Claim 8

Apparatus as recited in claim 2 wherein the temporary storage means includes gateable circuit means for presenting a relatively small time constant to said other electrode of the fast recovery diode while the storage arrangement is operating in the holding mode for presenting a relatively large time constant to said other electrode while the storage arrangement is operating in the shifting mode.

Claim 9

A shift register of the type comprising a plurality of cascaded stages; wherein each stage comprises: a bistable storage element having an input node and an output node; and coupling means including a series circuit comprising: a fast recovery diode having at least two electrodes, one of which is coupled to the output node of the bistable storage element; a transistor, the base electrode of which is coupled to the other electrode of the fast recover diode; and a second diode having at least two electrodes, one of which is coupled to an output electrode of the transistor, and the other of which is coupled to the input node of the bistable storage element in the next succeeding stage.

Claim 10

A shift register of the type comprising a plurality of cascaded stages; wherein each stage comprises: a bistable storage element having an input node and an output node; and coupling means including a series circuit comprising: a fast recovery diode having at least two electrodes, one of which is coupled to the output node of the bistable storage element; a transistor, the base electrode of which is coupled to the other electrode of the fast recover diode; and a second diode having at least two electrodes, one of which is coupled to an output electrode of the transistor, and the other of which is coupled to the input node of the bistable storage element in the next succeeding stage.

Claim 11

A shift register as recited in claim 7 further characterized in that the time constant of the circuitry attached to said one electrode of the fast recovery diode is smaller than the time constant of the circuitry attached to said other electrode of the fast recovery diode.

Claim 12

A shift register as recited in claim 7 wherein the fast recovery diode is a Schottky-barrier diode.

Claim 13

A shift register as recited in claim 7 in combination with means for causing the transistor to operate in the emitter-follower mode.

Claim 14

A shift register as recited in claim 7 in combination with an impedance in series with the emitter electrode of the transistor for causing the transistor to operate in the emitter-follower mode.

Claim 15

A shift register as recited in claim 7 wherein: the bistable storage element of the stage includes a control node adapted for connection to a source of pulses for controlling the holding and shifting of data; and the transistor is connected in combination with gateable circuit means for presenting a relatively small time constant to said other electrode of the fast recovery diode while the flip-flop is operating in the holding mode and for presenting a relatively large time constant to that electrode while the flip-flop is operating in the shifting mode.