Patent US3046530A successfully refreshed from Google Patents.
Patent US3612906A successfully refreshed from Google Patents.
US3612906A
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US
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Pulse synchronizer
Assignee: United States Department of the Navy
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Filing: 1970-09-28
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Granted: 1971-10-12
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Expires: 1990-09-28
Abstract
Abstract A pulse synchronizer employing two bistable flip-flops and a NAND gate is used to pass the first complete clock pulse which arrives after the incidence of a sample pulse.
Inventors
- 👤 Peter D Kennedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:49
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
116 words
In a synchronizing system, the improvement comprising: a first synchronous flip-flop, a second synchronous flip-flop, said flip-flops each having a clock input terminal, a set control input terminal, a direct set input terminal, a direct reset input terminal, and a first and a second complementary output terminal, a NAND gate, means connecting an output of each of said flip-flops to inputs of said NAND gate, means for furnishing clock pulses to said NAND gate, means for furnishing sample pulses to said first flip-flop, and connecting means whereby said NAND gate is enabled by said flip-flops to pass the first complete clock pulse arriving after the incidence of a sample pulse, to the output of said system.
Claim 2
Dependent Claim
116 words
In a synchronizing system, the improvement comprising: a first synchronous flip-flop, a second synchronous flip-flop, said flip-flops each having a clock input terminal, a set control input terminal, a direct set input terminal, a direct reset input terminal, and a first and a second complementary output terminal, a NAND gate, means connecting an output of each of said flip-flops to inputs of said NAND gate, means for furnishing clock pulses to said NAND gate, means for furnishing sample pulses to said first flip-flop, and connecting means whereby said NAND gate is enabled by said flip-flops to pass the first complete clock pulse arriving after the incidence of a sample pulse, to the output of said system.
Claim 3
Dependent Claim
103 words
The apparatus of claim 1, a first output of sAid first flip-flop being connected to an input of said NAND gate to enable said gate when in a reset condition, a second output of said second flip-flop being connected to an input of said NAND gate to enable said gate when in a set condition, said connecting means including means for supplying sample pulses to the clock input of said first flip-flop, and to the direct set input of said second flip-flop, and means for supplying clock pulses to the set control input and to the direct reset input of said first flip-flop.
Claim 4
Dependent Claim
83 words
The apparatus of claim 2 and including a feedback connection from the output of said NAND gate to the clock input of said second flip-flop, a first inverter in said feedback connection to invert a negative output pulse from said NAND gate to furnish a positive going pulse to the clock input of said second flip-flop, said second flip-flop being adapted to reset at the trailing edge of said positive going pulse, and a second inverter means arranged to invert said sample pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-11 | 1975-04-12 | 1975-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-11 | 1979-04-12 | 1979-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-11 | 1983-04-12 | 1983-10-12 | $7700.00 | Window Closed / Lapsed |